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author | Christian Menard <christian.menard@tu-dresden.de> | 2013-11-26 17:51:07 +0100 |
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committer | Christian Menard <christian.menard@tu-dresden.de> | 2013-11-26 17:51:07 +0100 |
commit | d4f205ea2ff2800b253d4681afaa6af330bfa33b (patch) | |
tree | 91a4849143127b37fa3d536aca32ea8074615ad1 /src/arch/x86/isa/insts | |
parent | e5d63d05354b7dc03b35e99d1f7b5aa80ec6fff5 (diff) | |
download | gem5-d4f205ea2ff2800b253d4681afaa6af330bfa33b.tar.xz |
x86: Implementation of Int3 and Int_Ib in long mode
This is an implementation of the x86 int3 and int immediate
instructions for long mode according to 'AMD64 Programmers Manual
Volume 3'.
Diffstat (limited to 'src/arch/x86/isa/insts')
-rw-r--r-- | src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 19a344008..d50e40e61 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py @@ -221,6 +221,34 @@ skipSegmentSquashing: def macroop IRET_VIRT { panic "Virtual mode iret isn't implemented!" }; + +def macroop INT3 { + + limm t1, 0x03, dataSize=8 + + rdip t7 + + # Are we in long mode? + rdm5reg t5 + andi t0, t5, 0x1, flags=(EZF,) + br rom_label("longModeSoftInterrupt"), flags=(CEZF,) + br rom_label("legacyModeInterrupt") +}; + +def macroop INT_I { + + #load the byte-sized interrupt vector specified in the instruction + .adjust_imm trimImm(8) + limm t1, imm, dataSize=8 + + rdip t7 + + # Are we in long mode? + rdm5reg t5 + andi t0, t5, 0x1, flags=(EZF,) + br rom_label("longModeSoftInterrupt"), flags=(CEZF,) + br rom_label("legacyModeInterrupt") +}; ''' #let {{ # class INT(Inst): |