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authorGabe Black <gblack@eecs.umich.edu>2007-07-24 15:07:03 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-24 15:07:03 -0700
commit28614addffabd2bd8c12b7fdd97815e1579f11bb (patch)
tree5b5b628ba8a136ba62db2fa2f3cc94e86bac6608 /src/arch/x86/isa/insts
parentf8f7f994b812dbf1e1cdd85cdd4814334b78239f (diff)
downloadgem5-28614addffabd2bd8c12b7fdd97815e1579f11bb.tar.xz
Implement cdqe and cqo, which are also called cbw and cwde, and cwd and cdq respectively, depending on the operand size.
--HG-- extra : convert_revision : 67ac035c68608d7260c21ce32009b344f3834e46
Diffstat (limited to 'src/arch/x86/isa/insts')
-rw-r--r--src/arch/x86/isa/insts/data_conversion/sign_extension.py13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/arch/x86/isa/insts/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/data_conversion/sign_extension.py
index e96eee694..6a2612c3c 100644
--- a/src/arch/x86/isa/insts/data_conversion/sign_extension.py
+++ b/src/arch/x86/isa/insts/data_conversion/sign_extension.py
@@ -53,7 +53,18 @@
#
# Authors: Gabe Black
-microcode = ""
+microcode = '''
+def macroop CDQE_R {
+ sext reg, reg, "env.dataSize << 2"
+};
+
+def macroop CQO_R_R {
+ # A shift might be slower than, for example, an explicit sign extension,
+ # so it might be worthwhile to try to find an alternative.
+ mov regm, regm, reg
+ sra regm, regm, "env.dataSize * 8 - 1"
+};
+'''
#let {{
# class CBW(Inst):
# "GenFault ${new UnimpInstFault}"