Fixed the distinction between far and near versions of jmp, call and ret. Implemented some shifts, rotates, and pushes.

--HG--
extra : convert_revision : fcb06189ff213e82da16ac43231feb308cb3a285

5 files changed, 143 insertions, 7 deletions

diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py
index c40080d85..c5bb66e58 100644
--- a/src/arch/x86/isa/insts/control_transfer/call.py
+++ b/src/arch/x86/isa/insts/control_transfer/call.py
@@ -59,11 +59,46 @@ def macroop CALL_NEAR_I
     # Make the default data size of calls 64 bits in 64 bit mode
     .adjust_env oszIn64Override
 
-    limm t2, imm
+    limm t1, imm
+    rdip t7
+    subi rsp, rsp, dsz
+    st t7, ss, [0, t0, rsp]
+    wrip t7, t1
+};
+
+def macroop CALL_NEAR_R
+{
+    # Make the default data size of calls 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
     rdip t1
     subi rsp, rsp, dsz
     st t1, ss, [0, t0, rsp]
-    wrip t1, t2
+    wripi reg, 0
+};
+
+def macroop CALL_NEAR_M
+{
+    # Make the default data size of calls 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    subi rsp, rsp, dsz
+    st t7, ss, [0, t0, rsp]
+    wripi t1, 0
+};
+
+def macroop CALL_NEAR_P
+{
+    # Make the default data size of calls 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    subi rsp, rsp, dsz
+    st t7, ss, [0, t0, rsp]
+    wripi t1, 0
 };
 '''
 #let {{
diff --git a/src/arch/x86/isa/insts/control_transfer/jump.py b/src/arch/x86/isa/insts/control_transfer/jump.py
index 489eb9e39..158861a3d 100644
--- a/src/arch/x86/isa/insts/control_transfer/jump.py
+++ b/src/arch/x86/isa/insts/control_transfer/jump.py
@@ -235,4 +235,10 @@ def macroop JMP_M
     wripi t1, 0
 };
 
+def macroop JMP_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    wripi t1, 0
+};
 '''
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index 585437b8c..c381dc4f4 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -69,6 +69,25 @@ def macroop PUSH_R {
     subi rsp, rsp, dsz
     st reg, ss, [0, t0, rsp]
 };
+
+def macroop PUSH_M {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    ld t1, ds, [scale, index, base], disp
+    subi rsp, rsp, dsz
+    st t1, ss, [0, t0, rsp]
+};
+
+def macroop PUSH_P {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    subi rsp, rsp, dsz
+    st t1, ss, [0, t0, rsp]
+};
 '''
 #let {{
 #    class POPA(Inst):
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
index e3aaf0043..5330b1ac5 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
@@ -53,14 +53,50 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop ROL_R_I
+{
+    rol reg, reg, imm
+};
+
+def macroop ROL_M_I
+{
+    ld t1, ds, [scale, index, base], disp
+    rol t1, t1, imm
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROL_P_I
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rol t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROR_R_I
+{
+    ror reg, reg, imm
+};
+
+def macroop ROR_M_I
+{
+    ld t1, ds, [scale, index, base], disp
+    ror t1, t1, imm
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROR_P_I
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    ror t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+'''
 #let {{
 #    class RCL(Inst):
 #	"GenFault ${new UnimpInstFault}"
 #    class RCR(Inst):
 #	"GenFault ${new UnimpInstFault}"
-#    class ROL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class ROR(Inst):
-#	"GenFault ${new UnimpInstFault}"
 #}};
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
index b1c86a921..5a04317d9 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
@@ -73,6 +73,46 @@ def macroop SAL_P_I
     sll t1, t1, imm
     st t1, ds, [0, t0, t7], disp
 };
+
+def macroop SHR_R_I
+{
+    srl reg, reg, imm
+};
+
+def macroop SHR_M_I
+{
+    ld t1, ds, [scale, index, base], disp
+    srl t1, t1, imm
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SHR_P_I
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srl t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAR_R_I
+{
+    sra reg, reg, imm
+};
+
+def macroop SAR_M_I
+{
+    ld t1, ds, [scale, index, base], disp
+    sra t1, t1, imm
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAR_P_I
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sra t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
 '''
 #let {{
 #    class SAL(Inst):