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authorNilay Vaish <nilay@cs.wisc.edu>2014-01-27 18:50:52 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-01-27 18:50:52 -0600
commit5be0b846b1ca0131fc6c67c1ff7dcf64791ebc73 (patch)
tree237af620be866ac41bc92877057f3731d408c84b /src/arch/x86/isa/insts
parent4eb3b1ed0b0cb5182d92fd56c21b5ca003c0fda5 (diff)
downloadgem5-5be0b846b1ca0131fc6c67c1ff7dcf64791ebc73.tar.xz
x86: implements fxch instruction.
Diffstat (limited to 'src/arch/x86/isa/insts')
-rw-r--r--src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py17
1 files changed, 16 insertions, 1 deletions
diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py
index 982ac8e55..b6fbb01cc 100644
--- a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py
+++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py
@@ -36,5 +36,20 @@
# Authors: Gabe Black
microcode = '''
-# FXCH
+def macroop FXCH_R
+{
+ movfp ufp1, sti
+ movfp sti, st(0)
+ movfp st(0), ufp1
+};
+
+def macroop FXCH_M
+{
+ fault "new UnimpInstFault"
+};
+
+def macroop FXCH_P
+{
+ fault "new UnimpInstFault"
+};
'''