Merge from head.

--HG-- extra : convert_revision : af16bc685ea28e44b8120f16b72f60a21d68c1e2
author: Steve Reinhardt <stever@gmail.com> 2007-07-31 00:37:07 -0400
committer: Steve Reinhardt <stever@gmail.com> 2007-07-31 00:37:07 -0400
commit: c4c8a121863fcbde7ba67823f06a3f7564c27cba (patch)
tree: accca43f0d87a07f3bcedf46a88fd6e3a5e86167 /src/arch/x86/isa/insts
parent: 2f93db6f95b02d2bedf9571330a3185ac3fa7fa9 (diff)
parent: ae3e1d22fc3bfff8c246a0a743b77f4096d95b74 (diff)
download: gem5-c4c8a121863fcbde7ba67823f06a3f7564c27cba.tar.xz
7 files changed, 240 insertions, 64 deletions
diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index 7e5578a3c..de4996f54 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -56,20 +56,20 @@
 microcode = '''
 def macroop ADD_R_R
 {
-    add reg, reg, regm
+    add reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop ADD_R_I
 {
     limm t1, imm
-    add reg, reg, t1
+    add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop ADD_M_I
 {
     limm t2, imm
     ld t1, ds, [scale, index, base], disp
-    add t1, t1, t2
+    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -78,14 +78,14 @@ def macroop ADD_P_I
     rdip t7
     limm t2, imm
     ld t1, ds, [0, t0, t7], disp
-    add t1, t1, t2
+    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADD_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    add t1, t1, reg
+    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -93,52 +93,52 @@ def macroop ADD_P_R
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    add t1, t1, reg
+    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADD_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    add reg, reg, t1
+    add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop ADD_R_P
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    add reg, reg, t1
+    add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SUB_R_R
 {
-    sub reg, reg, regm
+    sub reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SUB_R_I
 {
     limm t1, imm
-    sub reg, reg, t1
+    sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SUB_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    sub reg, reg, t1
+    sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SUB_R_P
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sub reg, reg, t1
+    sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SUB_M_I
 {
     limm t2, imm
     ld t1, ds, [scale, index, base], disp
-    sub t1, t1, t2
+    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -147,14 +147,14 @@ def macroop SUB_P_I
     rdip t7
     limm t2, imm
     ld t1, ds, [0, t0, t7], disp
-    sub t1, t1, t2
+    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SUB_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    sub t1, t1, reg
+    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -162,26 +162,26 @@ def macroop SUB_P_R
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sub t1, t1, reg
+    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_R_R
 {
-    adc reg, reg, regm
+    adc reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop ADC_R_I
 {
     limm t1, imm
-    adc reg, reg, t1
+    adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop ADC_M_I
 {
     limm t2, imm
     ld t1, ds, [scale, index, base], disp
-    adc t1, t1, t2
+    adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -190,14 +190,14 @@ def macroop ADC_P_I
     rdip t7
     limm t2, imm
     ld t1, ds, [0, t0, t7], disp
-    adc t1, t1, t2
+    adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    adc t1, t1, reg
+    adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -205,52 +205,52 @@ def macroop ADC_P_R
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    adc t1, t1, reg
+    adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    adc reg, reg, t1
+    adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop ADC_R_P
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    adc reg, reg, t1
+    adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SBB_R_R
 {
-    sbb reg, reg, regm
+    sbb reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SBB_R_I
 {
     limm t1, imm
-    sbb reg, reg, t1
+    sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SBB_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    sbb reg, reg, t1
+    sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SBB_R_P
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sbb reg, reg, t1
+    sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SBB_M_I
 {
     limm t2, imm
     ld t1, ds, [scale, index, base], disp
-    sbb t1, t1, t2
+    sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -259,14 +259,14 @@ def macroop SBB_P_I
     rdip t7
     limm t2, imm
     ld t1, ds, [0, t0, t7], disp
-    sbb t1, t1, t2
+    sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SBB_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    sbb t1, t1, reg
+    sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -274,7 +274,7 @@ def macroop SBB_P_R
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sbb t1, t1, reg
+    sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
index 339e18cf8..5355775eb 100644
--- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
+++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
@@ -56,39 +56,137 @@
 microcode = '''
 
 #
+# Byte version of one operand unsigned multiply.
+#
+
+def macroop MUL_B_R
+{
+    mul1u rax, rax, reg, dataSize="2"
+};
+
+def macroop MUL_B_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mul1u rax, rax, t1, dataSize="2"
+};
+
+def macroop MUL_B_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    mul1u rax, rax, t1, dataSize="2"
+};
+
+#
+# One operand unsigned multiply.
+#
+
+def macroop MUL_R
+{
+    muleh rdx, rax, reg
+    mulel rax, rax, reg
+};
+
+def macroop MUL_M
+{
+    ld t1, ds, [scale, index, base], disp
+    muleh rdx, rax, t1
+    mulel rax, rax, t1
+};
+
+def macroop MUL_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    muleh rdx, rax, t1
+    mulel rax, rax, t1
+};
+
+#
+# Byte version of one operand signed multiply.
+#
+
+def macroop IMUL_B_R
+{
+    mul1s rax, rax, reg, dataSize="2"
+};
+
+def macroop IMUL_B_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mul1s rax, rax, t1, dataSize="2"
+};
+
+def macroop IMUL_B_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    mul1s rax, rax, t1, dataSize="2"
+};
+
+#
+# One operand signed multiply.
+#
+
+def macroop IMUL_R
+{
+    muleh rdx, rax, reg
+    mulel rax, rax, reg
+};
+
+def macroop IMUL_M
+{
+    ld t1, ds, [scale, index, base], disp
+    muleh rdx, rax, t1
+    mulel rax, rax, t1
+};
+
+def macroop IMUL_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    muleh rdx, rax, t1
+    mulel rax, rax, t1
+};
+
+#
 # Two operand signed multiply. These should set the CF and OF flags if the
 # result is too large for the destination register
 #
 
 def macroop IMUL_R_R
 {
-    mul1s reg, reg, regm
+    mulel reg, reg, regm
 };
 
 def macroop IMUL_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    mul1s reg, reg, t1
+    mulel reg, reg, t1
 };
 
 def macroop IMUL_R_P
 {
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    mul1s reg, reg, t1
+    mulel reg, reg, t1
 };
 
+#
+# Three operand signed multiply.
+#
+
 def macroop IMUL_R_R_I
 {
     limm t1, imm
-    mul1s reg, regm, t1
+    mulel reg, regm, t1
 };
 
 def macroop IMUL_R_M_I
 {
     limm t1, imm
     ld t2, ds, [scale, index, base], disp
-    mul1s reg, t2, t1
+    mulel reg, t2, t1
 };
 
 def macroop IMUL_R_P_I
@@ -96,7 +194,54 @@ def macroop IMUL_R_P_I
     rdip t7
     limm t1, imm
     ld t2, ds, [0, t0, t7]
-    mul1s reg, t2, t1
+    mulel reg, t2, t1
+};
+
+#
+# One byte version of unsigned division
+#
+
+def macroop DIV_B_R
+{
+    div1 rax, rax, reg
+};
+
+def macroop DIV_B_M
+{
+    ld t1, ds, [scale, index, base], disp
+    div1 rax, rax, t1
+};
+
+def macroop DIV_B_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    div1 rax, rax, t1
+};
+
+#
+# Unsigned division
+#
+
+def macroop DIV_R
+{
+    divr rdx, rax, reg
+    divq rax, rax, reg
+};
+
+def macroop DIV_M
+{
+    ld t1, ds, [scale, index, base], disp
+    divr rdx, rax, t1
+    divq rax, rax, t1
+};
+
+def macroop DIV_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    divr rdx, rax, t1
+    divq rax, rax, t1
 };
 '''
 #let {{
diff --git a/src/arch/x86/isa/insts/control_transfer/jump.py b/src/arch/x86/isa/insts/control_transfer/jump.py
index 158861a3d..0df84cbe8 100644
--- a/src/arch/x86/isa/insts/control_transfer/jump.py
+++ b/src/arch/x86/isa/insts/control_transfer/jump.py
@@ -226,17 +226,26 @@ def macroop JMP_I
 
 def macroop JMP_R
 {
+    # Make the default data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
     wripi reg, 0
 };
 
 def macroop JMP_M
 {
+    # Make the default data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
     ld t1, ds, [scale, index, base], disp
     wripi t1, 0
 };
 
 def macroop JMP_P
 {
+    # Make the default data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
     rdip t7
     ld t1, ds, [0, t0, t7], disp
     wripi t1, 0
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index 1c13b44b4..082e24485 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -141,6 +141,15 @@ def macroop POPA {
     ld rax, ss, [0, t0, rsp], "7 * env.dataSize"
     addi rsp, rsp, "8 * env.dataSize"
 };
+
+def macroop LEAVE {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    mov rsp, rsp, rbp
+    ld rbp, ss, [0, t0, rsp]
+    addi rsp, rsp, dsz
+};
 '''
 #let {{
 #    class ENTER(Inst):
diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py
index dcaf9778e..fc8b17629 100644
--- a/src/arch/x86/isa/insts/load_effective_address.py
+++ b/src/arch/x86/isa/insts/load_effective_address.py
@@ -60,6 +60,6 @@ def macroop LEA_R_M {
 
 def macroop LEA_R_P {
     rdip t7
-    lea reg, ds, [scale, index, base], disp
+    lea reg, ds, [0, t0, t7], disp
 };
 '''
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index bbc15f8fa..81a4730de 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -56,14 +56,14 @@
 microcode = '''
 def macroop OR_R_R
 {
-    or reg, reg, regm
+    or reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop OR_M_I
 {
     limm t2, imm
     ld t1, ds, [scale, index, base], disp
-    or t1, t1, t2
+    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -72,14 +72,14 @@ def macroop OR_P_I
     limm t2, imm
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    or t1, t1, t2
+    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop OR_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    or t1, t1, reg
+    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -87,45 +87,45 @@ def macroop OR_P_R
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    or t1, t1, reg
+    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop OR_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    or reg, reg, t1
+    or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop OR_R_P
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    or reg, reg, t1
+    or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop OR_R_I
 {
     limm t1, imm
-    or reg, reg, t1
+    or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop XOR_R_R
 {
-    xor reg, reg, regm
+    xor reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop XOR_R_I
 {
     limm t1, imm
-    xor reg, reg, t1
+    xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop XOR_M_I
 {
     limm t2, imm
     ld t1, ds, [scale, index, base], disp
-    xor t1, t1, t2
+    xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -134,14 +134,14 @@ def macroop XOR_P_I
     limm t2, imm
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    xor t1, t1, t2
+    xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
 def macroop XOR_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    xor t1, t1, reg
+    xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -149,52 +149,52 @@ def macroop XOR_P_R
 {
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    xor t1, t1, reg
+    xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
 def macroop XOR_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    xor reg, reg, t1
+    xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop XOR_R_P
 {
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    xor reg, reg, t1
+    xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_R_R
 {
-    and reg, reg, regm
+    and reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    and reg, reg, t1
+    and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_R_P
 {
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    and reg, reg, t1
+    and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_R_I
 {
     limm t1, imm
-    and reg, reg, t1
+    and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_M_I
 {
     ld t2, ds, [scale, index, base], disp
     limm t1, imm
-    and t2, t2, t1
+    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
     st t2, ds, [scale, index, base], disp
 };
 
@@ -203,14 +203,14 @@ def macroop AND_P_I
     rdip t7
     ld t2, ds, [scale, index, base], disp
     limm t1, imm
-    and t2, t2, t1
+    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
     st t2, ds, [scale, index, base], disp
 };
 
 def macroop AND_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    and t1, t1, reg
+    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -218,7 +218,7 @@ def macroop AND_P_R
 {
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    and t1, t1, reg
+    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
diff --git a/src/arch/x86/isa/insts/processor_information.py b/src/arch/x86/isa/insts/processor_information.py
index b9c8a407e..f7ef4db98 100644
--- a/src/arch/x86/isa/insts/processor_information.py
+++ b/src/arch/x86/isa/insts/processor_information.py
@@ -53,7 +53,20 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop CPUID_R {
+    #
+    # For now, the CPUID function number will be hard wired to 0x8000_0000.
+    # Getting it to work more robustly will likely require microcode branching
+    # which probably doesn't work at the moment.
+    #
+
+    limm rax, 0x80000018, dataSize=4
+    limm rbx, 0x68747541, dataSize=4
+    limm rdx, 0x69746e65, dataSize=4
+    limm rcx, 0x444d4163, dataSize=4
+};
+'''
 #let {{
 #    class CPUID(Inst):
 #	"GenFault ${new UnimpInstFault}"
author	Steve Reinhardt <stever@gmail.com>	2007-07-31 00:37:07 -0400
committer	Steve Reinhardt <stever@gmail.com>	2007-07-31 00:37:07 -0400
commit	c4c8a121863fcbde7ba67823f06a3f7564c27cba (patch)
tree	accca43f0d87a07f3bcedf46a88fd6e3a5e86167 /src/arch/x86/isa/insts
parent	2f93db6f95b02d2bedf9571330a3185ac3fa7fa9 (diff)
parent	ae3e1d22fc3bfff8c246a0a743b77f4096d95b74 (diff)
download	gem5-c4c8a121863fcbde7ba67823f06a3f7564c27cba.tar.xz