x86 fixes

Make the emulation environment consider the rex prefix.
Implement and hook in forms of j, jmp, cmp, syscall, movzx
Added a format for an instruction to carry a call to the SE mode syscalls system
Made memory instructions which refer to the rip do so directly
Made the operand size overridable in the microassembly
Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on
Added an explicit "rax" operand for the syscall format
Implemented syscall returns.

--HG--
extra : convert_revision : ae84bd8c6a1d400906e17e8b8c4185f2ebd4c5f2

4 files changed, 119 insertions, 11 deletions

diff --git a/src/arch/x86/isa/insts/compare_and_test/compare.py b/src/arch/x86/isa/insts/compare_and_test/compare.py
index 12b5b859f..ba421a520 100644
--- a/src/arch/x86/isa/insts/compare_and_test/compare.py
+++ b/src/arch/x86/isa/insts/compare_and_test/compare.py
@@ -53,8 +53,10 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class CMP(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop CMP_R_I
+{
+    limm t1, imm
+    sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
+};
+'''
diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py
index 1d2364f0f..8da33899a 100644
--- a/src/arch/x86/isa/insts/compare_and_test/test.py
+++ b/src/arch/x86/isa/insts/compare_and_test/test.py
@@ -63,7 +63,7 @@ def macroop TEST_M_R
 def macroop TEST_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     and t0, t1, reg, flags=(SF, ZF, PF)
 };
 
@@ -82,7 +82,7 @@ def macroop TEST_M_I
 def macroop TEST_P_I
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     limm t2, imm
     and t0, t1, t2, flags=(SF, ZF, PF)
 };
diff --git a/src/arch/x86/isa/insts/control_transfer/jump.py b/src/arch/x86/isa/insts/control_transfer/jump.py
index 15f00e083..e01925f41 100644
--- a/src/arch/x86/isa/insts/control_transfer/jump.py
+++ b/src/arch/x86/isa/insts/control_transfer/jump.py
@@ -56,6 +56,9 @@
 microcode = '''
 def macroop JZ_I
 {
+    # Make the defualt data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
     rdip t1
     limm t2, imm
     wrip t1, t2, flags=(CZF,)
@@ -63,8 +66,53 @@ def macroop JZ_I
 
 def macroop JNZ_I
 {
+    # Make the defualt data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
     rdip t1
     limm t2, imm
     wrip t1, t2, flags=(nCZF,)
 };
+
+def macroop JNB_I
+{
+    # Make the default data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t1
+    limm t2, imm
+    wrip t1, t2, flags=(nCCF,)
+};
+
+def macroop JBE_I
+{
+    # Make the default data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t1
+    limm t2, imm
+    wrip t1, t2, flags=(CCvZF,)
+};
+
+def macroop JMP_I
+{
+    # Make the default data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t1
+    limm t2, imm
+    wrip t1, t2
+};
+
+def macroop JMP_R
+{
+    wripi reg, 0
+};
+
+def macroop JMP_M
+{
+    ld t1, ds, [scale, index, base], disp
+    wripi t1, 0
+};
+
 '''
diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py
index c85dd7cc4..9856b5051 100644
--- a/src/arch/x86/isa/insts/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/data_transfer/move.py
@@ -64,7 +64,7 @@ def macroop MOV_M_R {
 
 def macroop MOV_P_R {
     rdip t7
-    st reg, ds, [scale, index, base], disp
+    st reg, ds, [0, t0, t7], disp
 };
 
 def macroop MOV_R_M {
@@ -73,7 +73,7 @@ def macroop MOV_R_M {
 
 def macroop MOV_R_P {
     rdip t7
-    ld reg, ds, [scale, index, base], disp
+    ld reg, ds, [0, t0, t7], disp
 };
 
 def macroop MOV_R_I {
@@ -88,7 +88,7 @@ def macroop MOV_M_I {
 def macroop MOV_P_I {
     rdip t7
     limm t1, imm
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop MOVSXD_R_R {
@@ -102,9 +102,67 @@ def macroop MOVSXD_R_M {
 
 def macroop MOVSXD_R_P {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sext reg, t1, dsz
 };
+
+def macroop MOVZX_B_R_R {
+    mov reg, reg, t0
+    mov reg, reg, regm, dataSize=1
+};
+
+def macroop MOVZX_B_R_M {
+    mov reg, reg, t0
+    ld reg, ds, [scale, index, base], disp, dataSize=1
+};
+
+def macroop MOVZX_B_R_P {
+    rdip t7
+    mov reg, reg, t0
+    ld reg, ds, [0, t0, t7], disp, dataSize=1
+};
+
+def macroop MOVZX_B_M_R {
+    mov t1, t1, t0
+    mov t1, t1, reg, dataSize=1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop MOVZX_B_P_R {
+    rdip t7
+    mov t1, t1, t0
+    mov t1, t1, reg, dataSize=1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop MOVZX_W_R_R {
+    mov reg, reg, t0
+    mov reg, reg, regm, dataSize=2
+};
+
+def macroop MOVZX_W_R_M {
+    mov reg, reg, t0
+    ld reg, ds, [scale, index, base], disp, dataSize=2
+};
+
+def macroop MOVZX_W_R_P {
+    rdip t7
+    mov reg, reg, t0
+    ld reg, ds, [0, t0, t7], disp, dataSize=2
+};
+
+def macroop MOVZX_W_M_R {
+    mov t1, t1, t0
+    mov t1, t1, reg, dataSize=2
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop MOVZX_W_P_R {
+    rdip t7
+    mov t1, t1, t0
+    mov t1, t1, reg, dataSize=2
+    st t1, ds, [0, t0, t7], disp
+};
 '''
 #let {{
 #    class MOV(Inst):