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author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-19 14:18:46 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-19 14:18:46 +0000 |
commit | 053c715f213a6532b5644e46a5d04ef9e092139e (patch) | |
tree | 515d9abc887ddbc41431a902b1bf7c7ebb668776 /src/arch/x86/isa/insts | |
parent | 2d08ab0cc26fc2b03a575f054508abc035786a08 (diff) | |
parent | 6e286cddfaf6286f96e06c26266070f6fbbd7749 (diff) | |
download | gem5-053c715f213a6532b5644e46a5d04ef9e092139e.tar.xz |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : 2dfc24b0720b3b378858a289e4bb6f4ee7132b3d
Diffstat (limited to 'src/arch/x86/isa/insts')
-rw-r--r-- | src/arch/x86/isa/insts/data_transfer/move.py | 4 | ||||
-rw-r--r-- | src/arch/x86/isa/insts/data_transfer/stack_operations.py | 10 | ||||
-rw-r--r-- | src/arch/x86/isa/insts/logical.py | 16 |
3 files changed, 18 insertions, 12 deletions
diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py index 9d23b24e8..ff4af0af4 100644 --- a/src/arch/x86/isa/insts/data_transfer/move.py +++ b/src/arch/x86/isa/insts/data_transfer/move.py @@ -67,11 +67,11 @@ def macroop MOV_R_M { }; def macroop MOV_R_I { - limm "env.reg", "env.immediate" + limm "env.reg", "IMMEDIATE" }; def macroop MOV_M_I { - limm "env.reg", "env.immediate" + limm "env.reg", "IMMEDIATE" #Do a store to put the register operand into memory }; ''' diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py index b7ec0ec66..50b690354 100644 --- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py @@ -55,15 +55,21 @@ microcode = ''' def macroop POP_R { + + # Make the default data size of pops 64 bits in 64 bit mode .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" - # There needs to be a load here to actually "pop" the data + + ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] addi "INTREG_RSP", "INTREG_RSP", "env.dataSize" }; def macroop PUSH_R { + + # Make the default data size of pops 64 bits in 64 bit mode .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + subi "INTREG_RSP", "INTREG_RSP", "env.dataSize" - # There needs to be a store here to actually "push" the data + st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] }; ''' #let {{ diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py index ec0ed97b2..824c75053 100644 --- a/src/arch/x86/isa/insts/logical.py +++ b/src/arch/x86/isa/insts/logical.py @@ -61,34 +61,34 @@ def macroop XOR_R_R def macroop XOR_R_I { - limm "NUM_INTREGS", "env.immediate" - xor "env.reg", "env.reg", "NUM_INTREGS" + limm "NUM_INTREGS+1", "IMMEDIATE" + xor "env.reg", "env.reg", "NUM_INTREGS+1" }; def macroop XOR_M_R { #Do a load to get one of the sources - xor "NUM_INTREGS", "NUM_INTREGS", "env.reg" + xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg" #Do a store to write the destination }; def macroop XOR_R_M { #Do a load to get one of the sources - xor "env.reg", "env.reg", "NUM_INTREGS" + xor "env.reg", "env.reg", "NUM_INTREGS+1" }; def macroop AND_R_I { - limm "NUM_INTREGS", "env.immediate" - and "env.reg", "env.reg", "NUM_INTREGS" + limm "NUM_INTREGS+1", "IMMEDIATE" + and "env.reg", "env.reg", "NUM_INTREGS+1" }; def macroop AND_M_I { #Do a load to get one of the sources - limm "NUM_INTREGS", "env.immediate" - and "NUM_INTREGS", "NUM_INTREGS", "NUM_INTREGS+1" + limm "NUM_INTREGS+1", "IMMEDIATE" + and "NUM_INTREGS+1", "NUM_INTREGS+1", "NUM_INTREGS+2" #Do a store to write the destination }; ''' |