X86: Implement microops and instructions that manipulate the flags register.

--HG--
extra : convert_revision : 566841577bf4a98cac0b65292fe0f7daf89a9203

2 files changed, 32 insertions, 17 deletions

diff --git a/src/arch/x86/isa/insts/flags/set_and_clear.py b/src/arch/x86/isa/insts/flags/set_and_clear.py
index d70b95382..4c655e0b2 100644
--- a/src/arch/x86/isa/insts/flags/set_and_clear.py
+++ b/src/arch/x86/isa/insts/flags/set_and_clear.py
@@ -53,18 +53,39 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop CLD {
+    ruflags t1
+    limm t2, "~((uint64_t)DFBit)"
+    and t1, t1, t2
+    wruflags t1, t0
+};
+
+def macroop STD {
+    ruflags t1
+    limm t2, "DFBit"
+    or t1, t1, t2
+    wruflags t1, t0
+};
+
+def macroop CLC {
+    ruflags t1
+    andi t2, t1, "CFBit"
+    wruflags t1, t2
+};
+
+def macroop STC {
+    ruflags t1
+    ori t1, t1, "CFBit"
+    wruflags t1, t0
+};
+
+def macroop CMC {
+    ruflags t1
+    wruflagsi t1, "CFBit"
+};
+'''
 #let {{
-#    class CLC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class CMC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class STC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class CLD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class STD(Inst):
-#	"GenFault ${new UnimpInstFault}"
 #    class CLI(Inst):
 #	"GenFault ${new UnimpInstFault}"
 #    class STI(Inst):
diff --git a/src/arch/x86/isa/insts/semaphores.py b/src/arch/x86/isa/insts/semaphores.py
index 882213a3f..800f1b325 100644
--- a/src/arch/x86/isa/insts/semaphores.py
+++ b/src/arch/x86/isa/insts/semaphores.py
@@ -80,12 +80,6 @@ def macroop CMPXCHG_P_R {
 };
 '''
 #let {{
-#    class CMPXCHG(Inst):
-# 	"GenFault ${new UnimpInstFault}"
-#    class CMPXCHG8B(Inst):
-# 	"GenFault ${new UnimpInstFault}"
-#    class CMPXCHG16B(Inst):
-# 	"GenFault ${new UnimpInstFault}"
 #    class XADD(Inst):
 # 	"GenFault ${new UnimpInstFault}"
 #    class XCHG(Inst):