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authorGabe Black <gblack@eecs.umich.edu>2007-07-20 17:17:11 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-20 17:17:11 -0700
commit9093cb79a1a96867cae677f529a0d4bb19b288af (patch)
tree8f9f3ae4c1bd8c96900fb84bae00a7ab5b01d743 /src/arch/x86/isa/insts
parentc3669b892548ed3e1e8f4016f1e18202c5e7f484 (diff)
downloadgem5-9093cb79a1a96867cae677f529a0d4bb19b288af.tar.xz
Implement adc and sbb instructions and microops.
--HG-- extra : convert_revision : a2d3068c5b487f4fa7bf5c9cebba7753bc390bfa
Diffstat (limited to 'src/arch/x86/isa/insts')
-rw-r--r--src/arch/x86/isa/insts/arithmetic/add_and_subtract.py112
1 files changed, 112 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index a8bad4653..05aa6cd69 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -165,6 +165,118 @@ def macroop SUB_P_R
sub t1, t1, reg
st t1, ds, [scale, index, base], disp
};
+
+def macroop ADC_R_R
+{
+ adc reg, reg, regm
+};
+
+def macroop ADC_R_I
+{
+ limm t1, imm
+ adc reg, reg, t1
+};
+
+def macroop ADC_M_I
+{
+ limm t2, imm
+ ld t1, ds, [scale, index, base], disp
+ adc t1, t1, t2
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADC_P_I
+{
+ rdip t7
+ limm t2, imm
+ ld t1, ds, [scale, index, base], disp
+ adc t1, t1, t2
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADC_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ adc t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADC_P_R
+{
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ adc t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADC_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ adc reg, reg, t1
+};
+
+def macroop ADC_R_P
+{
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ adc reg, reg, t1
+};
+
+def macroop SBB_R_R
+{
+ sbb reg, reg, regm
+};
+
+def macroop SBB_R_I
+{
+ limm t1, imm
+ sbb reg, reg, t1
+};
+
+def macroop SBB_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ sbb reg, reg, t1
+};
+
+def macroop SBB_R_P
+{
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ sbb reg, reg, t1
+};
+
+def macroop SBB_M_I
+{
+ limm t2, imm
+ ld t1, ds, [scale, index, base], disp
+ sbb t1, t1, t2
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop SBB_P_I
+{
+ rdip t7
+ limm t2, imm
+ ld t1, ds, [scale, index, base], disp
+ sbb t1, t1, t2
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop SBB_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ sbb t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop SBB_P_R
+{
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ sbb t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
'''
#let {{
# class ADC(Inst):