X86: Reorganize segmentation and implement segment selector movs.

--HG--
extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8

2 files changed, 110 insertions, 8 deletions

diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
index a15fc21ef..aaddcf962 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -192,6 +192,108 @@ def macroop MOVZX_W_R_P {
 def macroop MOV_C_R {
     wrcr reg, regm
 };
+
+def macroop MOV_R_S {
+    rdsel reg, regm
+};
+
+def macroop MOV_M_S {
+    rdsel t1, reg
+    st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop MOV_P_S {
+    rdip t7
+    rdsel t1, reg
+    st t1, seg, riprel, disp, dataSize=2
+};
+
+def macroop MOV_REAL_S_R {
+    zext t2, regm, 15
+    slli t3, t2, 2, dataSize=8
+    wrsel reg, regm
+    wrbase reg, t3
+};
+
+def macroop MOV_REAL_S_M {
+    ld t1, seg, sib, disp, dataSize=2
+    zext t2, t1, 15
+    slli t3, t2, 2, dataSize=8
+    wrsel reg, t1
+    wrbase reg, t3
+};
+
+def macroop MOV_REAL_S_P {
+    rdip t7
+    ld t1, seg, riprel, disp, dataSize=2
+    zext t2, t1, 15
+    slli t3, t2, 2, dataSize=8
+    wrsel reg, t1
+    wrbase reg, t3
+};
+
+def macroop MOV_S_R {
+    chks t1, regm, flags=(EZF,), dataSize=8
+    bri t0, label("end"), flags=(CEZF,)
+    ld t2, flatseg, [1, t0, t1], addressSize=8, dataSize=8
+    wrdl reg, t2, regm
+end:
+    wrsel reg, regm
+};
+
+def macroop MOV_S_M {
+    ld t1, seg, sib, disp, dataSize=2
+    chks t2, t1, flags=(EZF,), dataSize=8
+    bri t0, label("end"), flags=(CEZF,)
+    ld t2, flatseg, [1, t0, t1], addressSize=8, dataSize=8
+    wrdl reg, t2, t1
+end:
+    wrsel reg, t1
+};
+
+def macroop MOV_S_P {
+    rdip t7
+    ld t1, seg, riprel, disp, dataSize=2
+    chks t2, t1, flags=(EZF,), dataSize=8
+    bri t0, label("end"), flags=(CEZF,)
+    ld t2, flatseg, [1, t0, t1], addressSize=8, dataSize=8
+    wrdl reg, t2, t1
+end:
+    wrsel reg, t1
+};
+
+def macroop MOVSS_S_R {
+    chks t1, regm, flags=(EZF,), dataSize=8
+    # This actually needs to use the selector as the error code, but it would
+    # be hard to get that information into the instruction at the moment.
+    fault "new GeneralProtection(0)", flags=(CEZF,)
+    ld t2, flatseg, [1, t0, t1], addressSize=8, dataSize=8
+    wrdl reg, t2, regm
+    wrsel reg, regm
+};
+
+def macroop MOVSS_S_M {
+    ld t1, seg, sib, disp, dataSize=2
+    chks t2, t1, flags=(EZF,), dataSize=8
+    # This actually needs to use the selector as the error code, but it would
+    # be hard to get that information into the instruction at the moment.
+    fault "new GeneralProtection(0)", flags=(CEZF,)
+    ld t2, flatseg, [1, t0, t1], addressSize=8, dataSize=8
+    wrdl reg, t2, t1
+    wrsel reg, t1
+};
+
+def macroop MOVSS_S_P {
+    rdip t7
+    ld t1, seg, riprel, disp, dataSize=2
+    chks t2, t1, flags=(EZF,), dataSize=8
+    # This actually needs to use the selector as the error code, but it would
+    # be hard to get that information into the instruction at the moment.
+    fault "new GeneralProtection(0)", flags=(CEZF,)
+    ld t2, flatseg, [1, t0, t1], addressSize=8, dataSize=8
+    wrdl reg, t2, t1
+    wrsel reg, t1
+};
 '''
 #let {{
 #    class MOVD(Inst):
diff --git a/src/arch/x86/isa/insts/system/segmentation.py b/src/arch/x86/isa/insts/system/segmentation.py
index e46941e53..97846f79c 100644
--- a/src/arch/x86/isa/insts/system/segmentation.py
+++ b/src/arch/x86/isa/insts/system/segmentation.py
@@ -62,8 +62,8 @@ def macroop LGDT_M
     ld t1, seg, sib, disp, dataSize=2
     # Get the base
     ld t2, seg, sib, 'adjustedDisp + 2'
-    wrbase gdtr, t2
-    wrlimit gdtr, t1
+    wrbase tsg, t2
+    wrlimit tsg, t1
 };
 
 def macroop LGDT_P
@@ -75,8 +75,8 @@ def macroop LGDT_P
     ld t1, seg, riprel, disp, dataSize=2
     # Get the base
     ld t2, seg, riprel, 'adjustedDisp + 2'
-    wrbase gdtr, t2
-    wrlimit gdtr, t1
+    wrbase tsg, t2
+    wrlimit tsg, t1
 };
 
 #
@@ -93,8 +93,8 @@ def macroop LGDT_16_M
     # Get the base
     ld t2, seg, sib, 'adjustedDisp + 2', dataSize=4
     zexti t2, t2, 23
-    wrbase gdtr, t2
-    wrlimit gdtr, t1
+    wrbase tsg, t2
+    wrlimit tsg, t1
 };
 
 def macroop LGDT_16_P
@@ -107,8 +107,8 @@ def macroop LGDT_16_P
     # Get the base
     ld t2, seg, riprel, 'adjustedDisp + 2', dataSize=4
     zexti t2, t2, 23
-    wrbase gdtr, t2
-    wrlimit gdtr, t1
+    wrbase tsg, t2
+    wrlimit tsg, t1
 };
 
 def macroop LIDT_M