diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:59 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:59 -0800 |
| commit | f1f5dd79bf8c2cf2ef64cc1432a4a0601d475e72 (patch) | |
| tree | 7215bb386591b8ff8d3ce53cefd40599c1a44c2a /src/arch/x86/isa/insts | |
| parent | 4d4d2883f9c84f0cebec4b65479c11540dbb36f7 (diff) | |
| download | gem5-f1f5dd79bf8c2cf2ef64cc1432a4a0601d475e72.tar.xz | |
X86: Implement the wrcr microop which writes a control register, and some control register work.
--HG--
extra : convert_revision : 3e9daef9cdd0665c033420e5b4f981649e9908ab
Diffstat (limited to 'src/arch/x86/isa/insts')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py index ada7f28a3..a15fc21ef 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py @@ -188,6 +188,10 @@ def macroop MOVZX_W_R_P { ld t1, seg, riprel, disp, dataSize=2 zexti reg, t1, 15 }; + +def macroop MOV_C_R { + wrcr reg, regm +}; ''' #let {{ # class MOVD(Inst): |