Implement a handful more instructions and differentiate macroops based on the operand types they expect.

--HG--
extra : convert_revision : f9c8e694a8c0eb33b988657dca03ab495b65bee8

3 files changed, 59 insertions, 3 deletions

diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py
index acfe2f516..9d23b24e8 100644
--- a/src/arch/x86/isa/insts/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/data_transfer/move.py
@@ -54,9 +54,26 @@
 # Authors: Gabe Black
 
 microcode = '''
-def macroop MOV{
+def macroop MOV_R_R {
     mov "env.reg", "env.reg", "env.regm"
 };
+
+def macroop MOV_M_R {
+    #Do a store to put the register operand into memory
+};
+
+def macroop MOV_R_M {
+    #Do a load to fill the register operand from memory
+};
+
+def macroop MOV_R_I {
+    limm "env.reg", "env.immediate"
+};
+
+def macroop MOV_M_I {
+    limm "env.reg", "env.immediate"
+    #Do a store to put the register operand into memory
+};
 '''
 #let {{
 #    class MOV(Inst):
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index fff0f749f..b7ec0ec66 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -54,11 +54,17 @@
 # Authors: Gabe Black
 
 microcode = '''
-def macroop POP {
+def macroop POP_R {
     .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
     # There needs to be a load here to actually "pop" the data
     addi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
 };
+
+def macroop PUSH_R {
+    .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
+    subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
+    # There needs to be a store here to actually "push" the data
+};
 '''
 #let {{
 #    class POP(Inst):
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index fee631da7..ec0ed97b2 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -54,10 +54,43 @@
 # Authors: Gabe Black
 
 microcode = '''
-def macroop XOR
+def macroop XOR_R_R
 {
     xor "env.reg", "env.reg", "env.regm"
 };
+
+def macroop XOR_R_I
+{
+    limm "NUM_INTREGS", "env.immediate"
+    xor "env.reg", "env.reg", "NUM_INTREGS"
+};
+
+def macroop XOR_M_R
+{
+    #Do a load to get one of the sources
+    xor "NUM_INTREGS", "NUM_INTREGS", "env.reg"
+    #Do a store to write the destination
+};
+
+def macroop XOR_R_M
+{
+    #Do a load to get one of the sources
+    xor "env.reg", "env.reg", "NUM_INTREGS"
+};
+
+def macroop AND_R_I
+{
+    limm "NUM_INTREGS", "env.immediate"
+    and "env.reg", "env.reg", "NUM_INTREGS"
+};
+
+def macroop AND_M_I
+{
+    #Do a load to get one of the sources
+    limm "NUM_INTREGS", "env.immediate"
+    and "NUM_INTREGS", "NUM_INTREGS", "NUM_INTREGS+1"
+    #Do a store to write the destination
+};
 '''
 #let {{
 #microcodeString = '''