Define and fill out a lot of different instructions and instruction versions. Added two of the shift microops.

--HG--
extra : convert_revision : 0b76953dbb1dc3366242d4d209cccebde86bbe4e

5 files changed, 249 insertions, 1 deletions

diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index 4d6e40c74..a8bad4653 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -54,6 +54,11 @@
 # Authors: Gabe Black
 
 microcode = '''
+def macroop ADD_R_R
+{
+    add reg, reg, regm
+};
+
 def macroop ADD_R_I
 {
     limm t1, imm
@@ -77,12 +82,58 @@ def macroop ADD_P_I
     st t1, ds, [scale, index, base], disp
 };
 
+def macroop ADD_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    add t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADD_P_R
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    add t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADD_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    add reg, reg, t1
+};
+
+def macroop ADD_R_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    add reg, reg, t1
+};
+
+def macroop SUB_R_R
+{
+    sub reg, reg, regm
+};
+
 def macroop SUB_R_I
 {
     limm t1, imm
     sub reg, reg, t1
 };
 
+def macroop SUB_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    sub reg, reg, t1
+};
+
+def macroop SUB_R_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    sub reg, reg, t1
+};
+
 def macroop SUB_M_I
 {
     limm t2, imm
@@ -99,6 +150,21 @@ def macroop SUB_P_I
     sub t1, t1, t2
     st t1, ds, [scale, index, base], disp
 };
+
+def macroop SUB_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    sub t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SUB_P_R
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    sub t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
 '''
 #let {{
 #    class ADC(Inst):
diff --git a/src/arch/x86/isa/insts/compare_and_test/compare.py b/src/arch/x86/isa/insts/compare_and_test/compare.py
index ba421a520..8f5890b23 100644
--- a/src/arch/x86/isa/insts/compare_and_test/compare.py
+++ b/src/arch/x86/isa/insts/compare_and_test/compare.py
@@ -54,6 +54,52 @@
 # Authors: Gabe Black
 
 microcode = '''
+def macroop CMP_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
+};
+
+def macroop CMP_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
+};
+
+def macroop CMP_M_I
+{
+    limm t2, imm
+    ld t1, ds, [scale, index, base], disp
+    sub t0, t1, t2, flags=(OF, SF, ZF, AF, PF, CF)
+};
+
+def macroop CMP_P_I
+{
+    limm t2, imm
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sub t0, t1, t2, flags=(OF, SF, ZF, AF, PF, CF)
+};
+
+def macroop CMP_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    sub t0, t1, reg, flags=(OF, SF, ZF, AF, PF, CF)
+};
+
+def macroop CMP_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sub t0, t1, reg, flags=(OF, SF, ZF, AF, PF, CF)
+};
+
+def macroop CMP_R_R
+{
+    sub t0, reg, regm, flags=(OF, SF, ZF, AF, PF, CF)
+};
+
 def macroop CMP_R_I
 {
     limm t1, imm
diff --git a/src/arch/x86/isa/insts/control_transfer/jump.py b/src/arch/x86/isa/insts/control_transfer/jump.py
index b191730d5..3d69643ae 100644
--- a/src/arch/x86/isa/insts/control_transfer/jump.py
+++ b/src/arch/x86/isa/insts/control_transfer/jump.py
@@ -104,6 +104,16 @@ def macroop JNBE_I
     wrip t1, t2, flags=(nCCvZF,)
 };
 
+def macroop JNLE_I
+{
+    # Make the default data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t1
+    limm t2, imm
+    wrip t1, t2, flags=(nCSxOvZF,)
+};
+
 def macroop JMP_I
 {
     # Make the default data size of jumps 64 bits in 64 bit mode
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index 2fd369d60..f99638cac 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -54,6 +54,62 @@
 # Authors: Gabe Black
 
 microcode = '''
+def macroop OR_R_R
+{
+    or reg, reg, regm
+};
+
+def macroop OR_M_I
+{
+    limm t2, imm
+    ld t1, ds, [scale, index, base], disp
+    or t1, t1, t2
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop OR_P_I
+{
+    limm t2, imm
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    or t1, t1, t2
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop OR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    or t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop OR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    or t1, t1, reg
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop OR_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    or reg, reg, t1
+};
+
+def macroop OR_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    or reg, reg, t1
+};
+
+def macroop OR_R_I
+{
+    limm t1, imm
+    or reg, reg, t1
+};
+
 def macroop XOR_R_R
 {
     xor reg, reg, regm
@@ -65,6 +121,23 @@ def macroop XOR_R_I
     xor reg, reg, t1
 };
 
+def macroop XOR_M_I
+{
+    limm t2, imm
+    ld t1, ds, [scale, index, base], disp
+    xor t1, t1, t2
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop XOR_P_I
+{
+    limm t2, imm
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    xor t1, t1, t2
+    st t1, ds, [scale, index, base], disp
+};
+
 def macroop XOR_M_R
 {
     ld t1, ds, [scale, index, base], disp
@@ -93,6 +166,24 @@ def macroop XOR_R_P
     xor reg, reg, t1
 };
 
+def macroop AND_R_R
+{
+    and reg, reg, regm
+};
+
+def macroop AND_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    and reg, reg, t1
+};
+
+def macroop AND_R_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    and reg, reg, t1
+};
+
 def macroop AND_R_I
 {
     limm t1, imm
@@ -115,6 +206,21 @@ def macroop AND_P_I
     and t2, t2, t1
     st t2, ds, [scale, index, base], disp
 };
+
+def macroop AND_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    and t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop AND_P_R
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    and t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
 '''
 #let {{
 #microcodeString = '''
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
index f72794657..b1c86a921 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
@@ -53,7 +53,27 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop SAL_R_I
+{
+    sll reg, reg, imm
+};
+
+def macroop SAL_M_I
+{
+    ld t1, ds, [scale, index, base], disp
+    sll t1, t1, imm
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAL_P_I
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sll t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+'''
 #let {{
 #    class SAL(Inst):
 #	"GenFault ${new UnimpInstFault}"