Merge python and x86 changes with cache branch

--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233

10 files changed, 1074 insertions, 109 deletions

diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index 05aa6cd69..7e5578a3c 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -77,9 +77,9 @@ def macroop ADD_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     add t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADD_M_R
@@ -92,9 +92,9 @@ def macroop ADD_M_R
 def macroop ADD_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     add t1, t1, reg
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADD_R_M
@@ -106,7 +106,7 @@ def macroop ADD_R_M
 def macroop ADD_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     add reg, reg, t1
 };
 
@@ -130,7 +130,7 @@ def macroop SUB_R_M
 def macroop SUB_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sub reg, reg, t1
 };
 
@@ -146,9 +146,9 @@ def macroop SUB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sub t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SUB_M_R
@@ -161,9 +161,9 @@ def macroop SUB_M_R
 def macroop SUB_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sub t1, t1, reg
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_R_R
@@ -189,9 +189,9 @@ def macroop ADC_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     adc t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_M_R
@@ -204,9 +204,9 @@ def macroop ADC_M_R
 def macroop ADC_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     adc t1, t1, reg
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_R_M
@@ -218,7 +218,7 @@ def macroop ADC_R_M
 def macroop ADC_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     adc reg, reg, t1
 };
 
@@ -242,7 +242,7 @@ def macroop SBB_R_M
 def macroop SBB_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sbb reg, reg, t1
 };
 
@@ -258,9 +258,9 @@ def macroop SBB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sbb t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SBB_M_R
@@ -273,20 +273,28 @@ def macroop SBB_M_R
 def macroop SBB_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sbb t1, t1, reg
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop NEG_R
+{
+    sub reg, t0, reg, flags=(CF,OF,SF,ZF,AF,PF)
+};
+
+def macroop NEG_M
+{
+    ld t1, ds, [scale, index, base], disp
+    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
     st t1, ds, [scale, index, base], disp
 };
+
+def macroop NEG_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
+    st t1, ds, [0, t0, t7], disp
+};
 '''
-#let {{
-#    class ADC(Inst):
-#	"Adc ^0 ^0 ^1"
-#    class ADD(Inst):
-#	"Add ^0 ^0 ^1"
-#    class SBB(Inst):
-#	"Sbb ^0 ^0 ^1"
-#    class SUB(Inst):
-#	"Sub ^0 ^0 ^1"
-#    class NEG(Inst):
-#	"Sub ^0 $0 ^0"
-#}};
diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
index eed39c10c..f53fa8f05 100644
--- a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
+++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
@@ -94,9 +94,3 @@ def macroop DEC_P
     st t1, ds, [0, t0, t7], disp
 };
 '''
-#let {{
-#    class DEC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class INC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
index 8697bef65..339e18cf8 100644
--- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
+++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
@@ -77,6 +77,27 @@ def macroop IMUL_R_P
     ld t1, ds, [scale, index, base], disp
     mul1s reg, reg, t1
 };
+
+def macroop IMUL_R_R_I
+{
+    limm t1, imm
+    mul1s reg, regm, t1
+};
+
+def macroop IMUL_R_M_I
+{
+    limm t1, imm
+    ld t2, ds, [scale, index, base], disp
+    mul1s reg, t2, t1
+};
+
+def macroop IMUL_R_P_I
+{
+    rdip t7
+    limm t1, imm
+    ld t2, ds, [0, t0, t7]
+    mul1s reg, t2, t1
+};
 '''
 #let {{
 #    class MUL(Inst):
diff --git a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
index 3d9250c2d..2008bf666 100644
--- a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
+++ b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
@@ -53,8 +53,340 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class SETcc(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop SETZ_R
+{
+    movi reg, reg, 1, flags=(CZF,)
+    movi reg, reg, 0, flags=(nCZF,)
+};
+
+def macroop SETZ_M
+{
+    movi t1, t1, 1, flags=(CZF,)
+    movi t1, t1, 0, flags=(nCZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETZ_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CZF,)
+    movi t1, t1, 0, flags=(nCZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNZ_R
+{
+    movi reg, reg, 1, flags=(nCZF,)
+    movi reg, reg, 0, flags=(CZF,)
+};
+
+def macroop SETNZ_M
+{
+    movi t1, t1, 1, flags=(nCZF,)
+    movi t1, t1, 0, flags=(CZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNZ_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCZF,)
+    movi t1, t1, 0, flags=(CZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETB_R
+{
+    movi reg, reg, 1, flags=(CCF,)
+    movi reg, reg, 0, flags=(nCCF,)
+};
+
+def macroop SETB_M
+{
+    movi t1, t1, 1, flags=(CCF,)
+    movi t1, t1, 0, flags=(nCCF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETB_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CCF,)
+    movi t1, t1, 0, flags=(nCCF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNB_R
+{
+    movi reg, reg, 1, flags=(nCCF,)
+    movi reg, reg, 0, flags=(CCF,)
+};
+
+def macroop SETNB_M
+{
+    movi t1, t1, 1, flags=(nCCF,)
+    movi t1, t1, 0, flags=(CCF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNB_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCCF,)
+    movi t1, t1, 0, flags=(CCF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETBE_R
+{
+    movi reg, reg, 1, flags=(CCvZF,)
+    movi reg, reg, 0, flags=(nCCvZF,)
+};
+
+def macroop SETBE_M
+{
+    movi t1, t1, 1, flags=(CCvZF,)
+    movi t1, t1, 0, flags=(nCCvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETBE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CCvZF,)
+    movi t1, t1, 0, flags=(nCCvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNBE_R
+{
+    movi reg, reg, 1, flags=(nCCvZF,)
+    movi reg, reg, 0, flags=(CCvZF,)
+};
+
+def macroop SETNBE_M
+{
+    movi t1, t1, 1, flags=(nCCvZF,)
+    movi t1, t1, 0, flags=(CCvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNBE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCCvZF,)
+    movi t1, t1, 0, flags=(CCvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETS_R
+{
+    movi reg, reg, 1, flags=(CSF,)
+    movi reg, reg, 0, flags=(nCSF,)
+};
+
+def macroop SETS_M
+{
+    movi t1, t1, 1, flags=(CSF,)
+    movi t1, t1, 0, flags=(nCSF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETS_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CSF,)
+    movi t1, t1, 0, flags=(nCSF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNS_R
+{
+    movi reg, reg, 1, flags=(nCSF,)
+    movi reg, reg, 0, flags=(CSF,)
+};
+
+def macroop SETNS_M
+{
+    movi t1, t1, 1, flags=(nCSF,)
+    movi t1, t1, 0, flags=(CSF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNS_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCSF,)
+    movi t1, t1, 0, flags=(CSF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETP_R
+{
+    movi reg, reg, 1, flags=(CPF,)
+    movi reg, reg, 0, flags=(nCPF,)
+};
+
+def macroop SETP_M
+{
+    movi t1, t1, 1, flags=(CPF,)
+    movi t1, t1, 0, flags=(nCPF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETP_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CPF,)
+    movi t1, t1, 0, flags=(nCPF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNP_R
+{
+    movi reg, reg, 1, flags=(nCPF,)
+    movi reg, reg, 0, flags=(CPF,)
+};
+
+def macroop SETNP_M
+{
+    movi t1, t1, 1, flags=(nCPF,)
+    movi t1, t1, 0, flags=(CPF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNP_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCPF,)
+    movi t1, t1, 0, flags=(CPF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETL_R
+{
+    movi reg, reg, 1, flags=(CSxOF,)
+    movi reg, reg, 0, flags=(nCSxOF,)
+};
+
+def macroop SETL_M
+{
+    movi t1, t1, 1, flags=(CSxOF,)
+    movi t1, t1, 0, flags=(nCSxOF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETL_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CSxOF,)
+    movi t1, t1, 0, flags=(nCSxOF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNL_R
+{
+    movi reg, reg, 1, flags=(nCSxOF,)
+    movi reg, reg, 0, flags=(CSxOF,)
+};
+
+def macroop SETNL_M
+{
+    movi t1, t1, 1, flags=(nCSxOF,)
+    movi t1, t1, 0, flags=(CSxOF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNL_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCSxOF,)
+    movi t1, t1, 0, flags=(CSxOF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETLE_R
+{
+    movi reg, reg, 1, flags=(CSxOvZF,)
+    movi reg, reg, 0, flags=(nCSxOvZF,)
+};
+
+def macroop SETLE_M
+{
+    movi t1, t1, 1, flags=(CSxOvZF,)
+    movi t1, t1, 0, flags=(nCSxOvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETLE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CSxOvZF,)
+    movi t1, t1, 0, flags=(nCSxOvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNLE_R
+{
+    movi reg, reg, 1, flags=(nCSxOvZF,)
+    movi reg, reg, 0, flags=(CSxOvZF,)
+};
+
+def macroop SETNLE_M
+{
+    movi t1, t1, 1, flags=(nCSxOvZF,)
+    movi t1, t1, 0, flags=(CSxOvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNLE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCSxOvZF,)
+    movi t1, t1, 0, flags=(CSxOvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETO_R
+{
+    movi reg, reg, 1, flags=(COF,)
+    movi reg, reg, 0, flags=(nCOF,)
+};
+
+def macroop SETO_M
+{
+    movi t1, t1, 1, flags=(COF,)
+    movi t1, t1, 0, flags=(nCOF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETO_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(COF,)
+    movi t1, t1, 0, flags=(nCOF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNO_R
+{
+    movi reg, reg, 1, flags=(nCOF,)
+    movi reg, reg, 0, flags=(COF,)
+};
+
+def macroop SETNO_M
+{
+    movi t1, t1, 1, flags=(nCOF,)
+    movi t1, t1, 0, flags=(COF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNO_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCOF,)
+    movi t1, t1, 0, flags=(COF,)
+    st t1, ds, [0, t0, t7], disp
+};
+'''
diff --git a/src/arch/x86/isa/insts/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/data_conversion/sign_extension.py
index e96eee694..6a2612c3c 100644
--- a/src/arch/x86/isa/insts/data_conversion/sign_extension.py
+++ b/src/arch/x86/isa/insts/data_conversion/sign_extension.py
@@ -53,7 +53,18 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop CDQE_R {
+    sext reg, reg, "env.dataSize << 2"
+};
+
+def macroop CQO_R_R {
+    # A shift might be slower than, for example, an explicit sign extension,
+    # so it might be worthwhile to try to find an alternative.
+    mov regm, regm, reg
+    sra regm, regm, "env.dataSize * 8 - 1"
+};
+'''
 #let {{
 #    class CBW(Inst):
 #	"GenFault ${new UnimpInstFault}"
diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
index 513e90c4e..17f8841f2 100644
--- a/src/arch/x86/isa/insts/data_transfer/conditional_move.py
+++ b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
@@ -53,8 +53,292 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class CMOVcc(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop CMOVZ_R_R
+{
+    mov reg, reg, regm, flags=(CZF,)
+};
+
+def macroop CMOVZ_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CZF,)
+};
+
+def macroop CMOVZ_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CZF,)
+};
+
+def macroop CMOVNZ_R_R
+{
+    mov reg, reg, regm, flags=(nCZF,)
+};
+
+def macroop CMOVNZ_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCZF,)
+};
+
+def macroop CMOVNZ_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCZF,)
+};
+
+def macroop CMOVB_R_R
+{
+    mov reg, reg, regm, flags=(CCF,)
+};
+
+def macroop CMOVB_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CCF,)
+};
+
+def macroop CMOVB_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CCF,)
+};
+
+def macroop CMOVNB_R_R
+{
+    mov reg, reg, regm, flags=(nCCF,)
+};
+
+def macroop CMOVNB_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCCF,)
+};
+
+def macroop CMOVNB_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCCF,)
+};
+
+def macroop CMOVBE_R_R
+{
+    mov reg, reg, regm, flags=(CCvZF,)
+};
+
+def macroop CMOVBE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CCvZF,)
+};
+
+def macroop CMOVBE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CCvZF,)
+};
+
+def macroop CMOVNBE_R_R
+{
+    mov reg, reg, regm, flags=(nCCvZF,)
+};
+
+def macroop CMOVNBE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCCvZF,)
+};
+
+def macroop CMOVNBE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCCvZF,)
+};
+
+def macroop CMOVS_R_R
+{
+    mov reg, reg, regm, flags=(CSF,)
+};
+
+def macroop CMOVS_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CSF,)
+};
+
+def macroop CMOVS_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CSF,)
+};
+
+def macroop CMOVNS_R_R
+{
+    mov reg, reg, regm, flags=(nCSF,)
+};
+
+def macroop CMOVNS_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCSF,)
+};
+
+def macroop CMOVNS_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCSF,)
+};
+
+def macroop CMOVP_R_R
+{
+    mov reg, reg, regm, flags=(CPF,)
+};
+
+def macroop CMOVP_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CPF,)
+};
+
+def macroop CMOVP_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CPF,)
+};
+
+def macroop CMOVNP_R_R
+{
+    mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVNP_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVNP_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVL_R_R
+{
+    mov reg, reg, regm, flags=(CSxOF,)
+};
+
+def macroop CMOVL_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CSxOF,)
+};
+
+def macroop CMOVL_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CSxOF,)
+};
+
+def macroop CMOVNL_R_R
+{
+    mov reg, reg, regm, flags=(nCSxOF,)
+};
+
+def macroop CMOVNL_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCSxOF,)
+};
+
+def macroop CMOVNL_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCSxOF,)
+};
+
+def macroop CMOVLE_R_R
+{
+    mov reg, reg, regm, flags=(CSxOvZF,)
+};
+
+def macroop CMOVLE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CSxOvZF,)
+};
+
+def macroop CMOVLE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CSxOvZF,)
+};
+
+def macroop CMOVNLE_R_R
+{
+    mov reg, reg, regm, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVNLE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVNLE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVO_R_R
+{
+    mov reg, reg, regm, flags=(COF,)
+};
+
+def macroop CMOVO_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(COF,)
+};
+
+def macroop CMOVO_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(COF,)
+};
+
+def macroop CMOVNO_R_R
+{
+    mov reg, reg, regm, flags=(nCOF,)
+};
+
+def macroop CMOVNO_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCOF,)
+};
+
+def macroop CMOVNO_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCOF,)
+};
+'''
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index c381dc4f4..889e7b88b 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -62,6 +62,25 @@ def macroop POP_R {
     addi rsp, rsp, dsz
 };
 
+def macroop POP_M {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    ld t1, ss, [0, t0, rsp]
+    addi rsp, rsp, dsz
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop POP_P {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t7
+    ld t1, ss, [0, t0, rsp]
+    addi rsp, rsp, dsz
+    st t1, ds, [0, t0, t7]
+};
+
 def macroop PUSH_R {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
@@ -70,6 +89,15 @@ def macroop PUSH_R {
     st reg, ss, [0, t0, rsp]
 };
 
+def macroop PUSH_I {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    limm t1, imm
+    subi rsp, rsp, dsz
+    st t1, ss, [0, t0, rsp]
+};
+
 def macroop PUSH_M {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
@@ -88,16 +116,32 @@ def macroop PUSH_P {
     subi rsp, rsp, dsz
     st t1, ss, [0, t0, rsp]
 };
+
+def macroop PUSHA {
+    st rax, ss, [0, t0, rsp], "-0 * env.dataSize"
+    st rcx, ss, [0, t0, rsp], "-1 * env.dataSize"
+    st rdx, ss, [0, t0, rsp], "-2 * env.dataSize"
+    st rbx, ss, [0, t0, rsp], "-3 * env.dataSize"
+    st rsp, ss, [0, t0, rsp], "-4 * env.dataSize"
+    st rbp, ss, [0, t0, rsp], "-5 * env.dataSize"
+    st rsi, ss, [0, t0, rsp], "-6 * env.dataSize"
+    st rdi, ss, [0, t0, rsp], "-7 * env.dataSize"
+    subi rsp, rsp, "8 * env.dataSize"
+};
+
+def macroop POPA {
+    st rdi, ss, [0, t0, rsp], "0 * env.dataSize"
+    st rsi, ss, [0, t0, rsp], "1 * env.dataSize"
+    st rbp, ss, [0, t0, rsp], "2 * env.dataSize"
+    st rsp, ss, [0, t0, rsp], "3 * env.dataSize"
+    st rbx, ss, [0, t0, rsp], "4 * env.dataSize"
+    st rdx, ss, [0, t0, rsp], "5 * env.dataSize"
+    st rcx, ss, [0, t0, rsp], "6 * env.dataSize"
+    st rax, ss, [0, t0, rsp], "7 * env.dataSize"
+    addi rsp, rsp, "8 * env.dataSize"
+};
 '''
 #let {{
-#    class POPA(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class POPAD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHA(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHAD(Inst):
-#	"GenFault ${new UnimpInstFault}"
 #    class ENTER(Inst):
 #	"GenFault ${new UnimpInstFault}"
 #    class LEAVE(Inst):
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index f99638cac..bbc15f8fa 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -221,16 +221,27 @@ def macroop AND_P_R
     and t1, t1, reg
     st t1, ds, [scale, index, base], disp
 };
+
+def macroop NOT_R
+{
+    limm t1, -1
+    xor reg, reg, t1
+};
+
+def macroop NOT_M
+{
+    limm t1, -1
+    ld t2, ds, [scale, index, base], disp
+    xor t2, t2, t1
+    st t2, ds, [scale, index, base], disp
+};
+
+def macroop NOT_P
+{
+    limm t1, -1
+    rdip t7
+    ld t2, ds, [0, t0, t7], disp
+    xor t2, t2, t1
+    st t2, ds, [0, t0, t7], disp
+};
 '''
-#let {{
-#microcodeString = '''
-#    def macroop OR
-#    {
-#	Or reg reg regm
-#    };
-#    def macroop NOT
-#    {
-#	Xor reg reg "0xFFFFFFFFFFFFFFFFULL"
-#    };
-#'''
-#}};
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
index 0988f8815..538e641ab 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
@@ -56,13 +56,13 @@
 microcode = '''
 def macroop ROL_R_I
 {
-    rol reg, reg, imm
+    roli reg, reg, imm
 };
 
 def macroop ROL_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    rol t1, t1, imm
+    roli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -70,19 +70,59 @@ def macroop ROL_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    rol t1, t1, imm
+    roli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROL_1_R
+{
+    roli reg, reg, 1
+};
+
+def macroop ROL_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    roli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROL_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    roli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROL_R_R
+{
+    rol reg, reg, regm
+};
+
+def macroop ROL_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    rol t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROL_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rol t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ROR_R_I
 {
-    ror reg, reg, imm
+    rori reg, reg, imm
 };
 
 def macroop ROR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    ror t1, t1, imm
+    rori t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -90,19 +130,59 @@ def macroop ROR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    ror t1, t1, imm
+    rori t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROR_1_R
+{
+    rori reg, reg, 1
+};
+
+def macroop ROR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    rori t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rori t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROR_R_R
+{
+    ror reg, reg, regm
+};
+
+def macroop ROR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    ror t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    ror t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop RCL_R_I
 {
-    rcl reg, reg, imm
+    rcli reg, reg, imm
 };
 
 def macroop RCL_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    rcl t1, t1, imm
+    rcli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -110,19 +190,59 @@ def macroop RCL_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    rcl t1, t1, imm
+    rcli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCL_1_R
+{
+    rcli reg, reg, 1
+};
+
+def macroop RCL_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    rcli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCL_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCL_R_R
+{
+    rcl reg, reg, regm
+};
+
+def macroop RCL_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    rcl t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCL_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcl t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop RCR_R_I
 {
-    rcr reg, reg, imm
+    rcri reg, reg, imm
 };
 
 def macroop RCR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    rcr t1, t1, imm
+    rcri t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -130,13 +250,47 @@ def macroop RCR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    rcr t1, t1, imm
+    rcri t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCR_1_R
+{
+    rcri reg, reg, 1
+};
+
+def macroop RCR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    rcri t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcri t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCR_R_R
+{
+    rcr reg, reg, regm
+};
+
+def macroop RCR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    rcr t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcr t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 '''
-#let {{
-#    class RCL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class RCR(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
index 5a04317d9..64eab3edc 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
@@ -56,13 +56,13 @@
 microcode = '''
 def macroop SAL_R_I
 {
-    sll reg, reg, imm
+    slli reg, reg, imm
 };
 
 def macroop SAL_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    sll t1, t1, imm
+    slli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -70,19 +70,59 @@ def macroop SAL_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sll t1, t1, imm
+    slli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAL_1_R
+{
+    slli reg, reg, 1
+};
+
+def macroop SAL_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    slli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAL_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    slli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAL_R_R
+{
+    sll reg, reg, regm
+};
+
+def macroop SAL_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    sll t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAL_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sll t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SHR_R_I
 {
-    srl reg, reg, imm
+    srli reg, reg, imm
 };
 
 def macroop SHR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    srl t1, t1, imm
+    srli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -90,19 +130,59 @@ def macroop SHR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    srl t1, t1, imm
+    srli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SHR_1_R
+{
+    srli reg, reg, 1
+};
+
+def macroop SHR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    srli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SHR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SHR_R_R
+{
+    srl reg, reg, regm
+};
+
+def macroop SHR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    srl t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SHR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srl t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SAR_R_I
 {
-    sra reg, reg, imm
+    srai reg, reg, imm
 };
 
 def macroop SAR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    sra t1, t1, imm
+    srai t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -110,21 +190,47 @@ def macroop SAR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sra t1, t1, imm
+    srai t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAR_1_R
+{
+    srai reg, reg, 1
+};
+
+def macroop SAR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    srai t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srai t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAR_R_R
+{
+    sra reg, reg, regm
+};
+
+def macroop SAR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    sra t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sra t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 '''
-#let {{
-#    class SAL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SAR(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHR(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHLD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHRD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};