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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-17 20:25:13 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-17 20:25:13 -0700 |
| commit | b315c3effc89127017c34b55908e7e63adca3f11 (patch) | |
| tree | 0673781b12ea95b6e7d97aae0277c38e9b785611 /src/arch/x86/isa/insts | |
| parent | 7fbd9e12961aaee1c81e723c4d40b70d5108845e (diff) | |
| download | gem5-b315c3effc89127017c34b55908e7e63adca3f11.tar.xz | |
X86: Implement STMXCSR.
Diffstat (limited to 'src/arch/x86/isa/insts')
| -rw-r--r-- | src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py index 687391b47..831a266c7 100644 --- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py +++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py @@ -54,6 +54,15 @@ # Authors: Gabe Black microcode = ''' -# STMXCSR +def macroop STMXCSR_M { + rdval t1, "InstRegIndex(MISCREG_MXCSR)" + st t1, seg, sib, disp +}; + +def macroop STMXCSR_P { + rdval t1, "InstRegIndex(MISCREG_MXCSR)" + rdip t7 + st t1, seg, riprel, disp +}; # LDMXCSR ''' |