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| author | Emilio Castillo <castilloe@unican.es> | 2015-01-10 14:30:53 -0600 |
|---|---|---|
| committer | Emilio Castillo <castilloe@unican.es> | 2015-01-10 14:30:53 -0600 |
| commit | 7bb65dd4345401f40eccb5c23b563558dfd9e854 (patch) | |
| tree | 275eabaa3852f0a3561c932d98d2ab2b98ca7ef5 /src/arch/x86/isa/insts | |
| parent | ec64b81a9d0de38c5e4ad32a80716ba12ef413fa (diff) | |
| download | gem5-7bb65dd4345401f40eccb5c23b563558dfd9e854.tar.xz | |
x86 : fxsave and fxrestore missing template code
This patch corrects the FXSAVE and FXRSTOR Macroops. The actual code used for
saving/restore the FP registers is in the file but it was not used.
The FXSAVE and FXRSTOR instructions are used in the kernel for saving and
loading the state of the mmx,xmm and fpu registers.
This operation is triggered in FS by issuing a Device Not Available Fault. The
cr0 register has a TS flag that is set upon each context change. Every time a
task access any FP related register (SIMD as well) if the TS flag is set to
one, the device not available fault is issued. The kernel saves the current
state of the registers, and restore the previous state of the currently running
task.
Right now Gem5 lacks of this capability. the Device Not Available Fault is
never issued, leading to several problems when different threads share the same
CPU and SMT is not used. The PARSEC Ferret benchmark is an example of this
behavior.
In order to test this a hack in the atomic cpu code was done to detect if a
static instruction has any FP operands and the cr0 reg TS bit is set. This
check must be done in the ISA dependent code. But it seems to be tricky to
access the cr0 register while executing an instruction.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/arch/x86/isa/insts')
| -rw-r--r-- | src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py index 2bb3e7a42..1017d519f 100644 --- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py +++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py @@ -105,7 +105,7 @@ fxsave32Template = """ rdval t1, "InstRegIndex(MISCREG_FOSEG)" st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 4", dataSize=2 -""" +""" + fxsaveCommonTemplate fxsave64Template = """ rdval t1, "InstRegIndex(MISCREG_FIOFF)" @@ -113,7 +113,7 @@ fxsave64Template = """ rdval t1, "InstRegIndex(MISCREG_FOOFF)" st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=8 -""" +""" + fxsaveCommonTemplate fxrstorCommonTemplate = """ ld t1, seg, %(mode)s, "DISPLACEMENT + 0", dataSize=2 @@ -149,7 +149,7 @@ fxrstor32Template = """ ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 4", dataSize=2 wrval "InstRegIndex(MISCREG_FOSEG)", t1 -""" +""" + fxrstorCommonTemplate fxrstor64Template = """ limm t2, 0, dataSize=8 @@ -161,7 +161,7 @@ fxrstor64Template = """ ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=8 wrval "InstRegIndex(MISCREG_FOOFF)", t1 wrval "InstRegIndex(MISCREG_FOSEG)", t2 -""" +""" + fxrstorCommonTemplate microcode = ''' def macroop FXSAVE_M { |