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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-01 17:09:08 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-01 17:09:08 -0800 |
| commit | 5a4eed5d34c814486086bf45d7750905de32d972 (patch) | |
| tree | f29003f1a2e6cf8072fb9c4c1514b4381807290f /src/arch/x86/isa/insts | |
| parent | 923a14dde749ad6b1887ccea764439a167555772 (diff) | |
| download | gem5-5a4eed5d34c814486086bf45d7750905de32d972.tar.xz | |
X86: All x86 fault classes now attempt to do something useful.
Diffstat (limited to 'src/arch/x86/isa/insts')
| -rw-r--r-- | src/arch/x86/isa/insts/romutil.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/insts/romutil.py b/src/arch/x86/isa/insts/romutil.py index ea41d2ca8..1345c3d05 100644 --- a/src/arch/x86/isa/insts/romutil.py +++ b/src/arch/x86/isa/insts/romutil.py @@ -95,7 +95,7 @@ def rom # If we're here, it's because the stack isn't being switched. # Set t6 to the new aligned rsp. - mov t6, rsp, dataSize=8 + mov t6, t6, rsp, dataSize=8 andi t6, t6, 0xF0, dataSize=1 subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8 |