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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-19 14:18:46 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-19 14:18:46 +0000 |
| commit | 053c715f213a6532b5644e46a5d04ef9e092139e (patch) | |
| tree | 515d9abc887ddbc41431a902b1bf7c7ebb668776 /src/arch/x86/isa/macroop.isa | |
| parent | 2d08ab0cc26fc2b03a575f054508abc035786a08 (diff) | |
| parent | 6e286cddfaf6286f96e06c26266070f6fbbd7749 (diff) | |
| download | gem5-053c715f213a6532b5644e46a5d04ef9e092139e.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : 2dfc24b0720b3b378858a289e4bb6f4ee7132b3d
Diffstat (limited to 'src/arch/x86/isa/macroop.isa')
| -rw-r--r-- | src/arch/x86/isa/macroop.isa | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 2d928d7c9..0cc818409 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -189,17 +189,18 @@ output header {{ { X86ISA::RegIndex reg; X86ISA::RegIndex regm; - uint64_t immediate; - uint64_t displacement; - int addressSize; + uint8_t scale; + X86ISA::RegIndex index; + X86ISA::RegIndex base; int dataSize; + int addressSize; + int stackSize; EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm, - uint64_t _immediate, uint64_t _displacement, - int _addressSize, int _dataSize) : + int _dataSize, int _addressSize, int _stackSize) : reg(_reg), regm(_regm), - immediate(_immediate), displacement(_displacement), - addressSize(_addressSize), dataSize(_dataSize) + dataSize(_dataSize), addressSize(_addressSize), + stackSize(_stackSize) {;} }; }}; @@ -211,17 +212,15 @@ let {{ self.regUsed = False self.regm = "0" self.regmUsed = False - self.immediate = "IMMEDIATE" - self.displacement = "DISPLACEMENT" self.addressSize = "ADDRSIZE" self.dataSize = "OPSIZE" + self.stackSize = "STACKSIZE" def getAllocator(self): return '''EmulEnv(%(reg)s, %(regm)s, - %(immediate)s, - %(displacement)s, + %(dataSize)s, %(addressSize)s, - %(dataSize)s)''' % \ + %(stackSize)s)''' % \ self.__dict__ def addReg(self, reg): if not self.regUsed: |