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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-19 14:18:25 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-19 14:18:25 +0000 |
| commit | 6e286cddfaf6286f96e06c26266070f6fbbd7749 (patch) | |
| tree | f318b62e376304d0b7f353a68794e4da160f5c8e /src/arch/x86/isa/macroop.isa | |
| parent | 8caef7d25a6a150fa6369234bbdc8c14ef637df8 (diff) | |
| download | gem5-6e286cddfaf6286f96e06c26266070f6fbbd7749.tar.xz | |
Get rid of the immediate and displacement components of the EmulEnv struct and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.
--HG--
extra : convert_revision : 0686296ca8b72940d961ecc6051063bfda1e932d
Diffstat (limited to 'src/arch/x86/isa/macroop.isa')
| -rw-r--r-- | src/arch/x86/isa/macroop.isa | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 2d928d7c9..0cc818409 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -189,17 +189,18 @@ output header {{ { X86ISA::RegIndex reg; X86ISA::RegIndex regm; - uint64_t immediate; - uint64_t displacement; - int addressSize; + uint8_t scale; + X86ISA::RegIndex index; + X86ISA::RegIndex base; int dataSize; + int addressSize; + int stackSize; EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm, - uint64_t _immediate, uint64_t _displacement, - int _addressSize, int _dataSize) : + int _dataSize, int _addressSize, int _stackSize) : reg(_reg), regm(_regm), - immediate(_immediate), displacement(_displacement), - addressSize(_addressSize), dataSize(_dataSize) + dataSize(_dataSize), addressSize(_addressSize), + stackSize(_stackSize) {;} }; }}; @@ -211,17 +212,15 @@ let {{ self.regUsed = False self.regm = "0" self.regmUsed = False - self.immediate = "IMMEDIATE" - self.displacement = "DISPLACEMENT" self.addressSize = "ADDRSIZE" self.dataSize = "OPSIZE" + self.stackSize = "STACKSIZE" def getAllocator(self): return '''EmulEnv(%(reg)s, %(regm)s, - %(immediate)s, - %(displacement)s, + %(dataSize)s, %(addressSize)s, - %(dataSize)s)''' % \ + %(stackSize)s)''' % \ self.__dict__ def addReg(self, reg): if not self.regUsed: |