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authorGabe Black <gblack@eecs.umich.edu>2007-09-04 23:32:18 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-09-04 23:32:18 -0700
commit8e3b199cb8fc0109b0bfe87905bb3253b4e7b8c7 (patch)
tree77126ed3bc26c1e36448b5e32b1da49b8f29b306 /src/arch/x86/isa/macroop.isa
parentaf4c04c426cca3b73e58ab7464119db28252984c (diff)
downloadgem5-8e3b199cb8fc0109b0bfe87905bb3253b4e7b8c7.tar.xz
X86: Add some SSE floating point/integer conversion microops.
--HG-- extra : convert_revision : 2a1aa16709db940f5f40bbd84ca082f26b03b9c5
Diffstat (limited to 'src/arch/x86/isa/macroop.isa')
-rw-r--r--src/arch/x86/isa/macroop.isa7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 3f33c8cfe..c9c33f981 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -221,6 +221,11 @@ let {{
self.dataSize = 1
elif self.size == 'd':
self.dataSize = 4
+ #This is for "double plus" which is normally a double word unless
+ #the REX W bit is set, in which case it's a quad word. It's used
+ #for some SSE instructions.
+ elif self.size == 'dp':
+ self.dataSize = "(REX_W ? 8 : 4)"
elif self.size == 'q':
self.dataSize = 8
elif self.size == 'v':
@@ -251,7 +256,7 @@ let {{
if not self.size:
self.size = size
else:
- if self.size is not size:
+ if self.size != size:
raise Exception, "Conflicting register sizes %s and %s!" %\
(self.size, size)
}};