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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-21 20:35:27 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-21 20:35:27 +0000 |
| commit | 70d6044527d6e6dfaf2de6674ae412706b6e131c (patch) | |
| tree | f4fc2b74cc2267d85f84db16694107a2bbbf973d /src/arch/x86/isa/microasm.isa | |
| parent | ec24de8b59e174b93b7c42669d71fe61db296688 (diff) | |
| download | gem5-70d6044527d6e6dfaf2de6674ae412706b6e131c.tar.xz | |
Make symbols for regular registers.
--HG--
extra : convert_revision : 28a6df1efe4298877dc2b20179caeb25dfdc4622
Diffstat (limited to 'src/arch/x86/isa/microasm.isa')
| -rw-r--r-- | src/arch/x86/isa/microasm.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 4e06f4391..ee2b92f53 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -91,6 +91,9 @@ let {{ "osz" : "env.operandSize", "ssz" : "env.stackSize" } + + for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): + assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() assembler.symbols.update(symbols) # Code literal which forces a default 64 bit operand size in 64 bit mode. |