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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-10-12 16:37:55 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-10-12 16:37:55 -0700 |
| commit | 9498e536c0231b808669f2bacb4c0628d1ec309a (patch) | |
| tree | 13edd1623e87077269a03b10a37a66bf61f4f969 /src/arch/x86/isa/microasm.isa | |
| parent | 8b35bd6fe79ce069428431a4edbe43b8373f7e87 (diff) | |
| download | gem5-9498e536c0231b808669f2bacb4c0628d1ec309a.tar.xz | |
X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.
--HG--
extra : convert_revision : ff893eb569313d8aecbfffb47bcbd1c2d65cd393
Diffstat (limited to 'src/arch/x86/isa/microasm.isa')
| -rw-r--r-- | src/arch/x86/isa/microasm.isa | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index c8bc36b69..50135e30c 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -106,6 +106,10 @@ let {{ assembler.symbols["riprel"] = \ ["1", assembler.symbols["t0"], assembler.symbols["t7"]] + # This segment selects an internal address space mapped to MSRs, + # CPUID info, etc. + assembler.symbols["intseg"] = "NUM_SEGMENTREGS" + for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() |