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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
| commit | e410a925df8d37f386c97dc7cdd9a78347ce4700 (patch) | |
| tree | b4102987453b1303051dfeea61aa1a45c2e5e75f /src/arch/x86/isa/microasm.isa | |
| parent | ced6cbcccf4540358093f060dad4d59ad6557d6a (diff) | |
| download | gem5-e410a925df8d37f386c97dc7cdd9a78347ce4700.tar.xz | |
X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
Diffstat (limited to 'src/arch/x86/isa/microasm.isa')
| -rw-r--r-- | src/arch/x86/isa/microasm.isa | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 213468b0b..5c567a30c 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -84,6 +84,7 @@ let {{ "regm" : "env.regm", "imm" : "IMMEDIATE", "disp" : "DISPLACEMENT", + "seg" : "env.seg", "scale" : "env.scale", "index" : "env.index", "base" : "env.base", @@ -91,10 +92,16 @@ let {{ "osz" : "env.operandSize", "ssz" : "env.stackSize" } + assembler.symbols.update(symbols) + + # Short hand for common scale-index-base combinations. + assembler.symbols["sib"] = \ + [symbols["scale"], symbols["index"], symbols["base"]] + assembler.symbols["riprel"] = \ + ["1", assembler.symbols["t0"], assembler.symbols["t7"]] for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() - assembler.symbols.update(symbols) for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'): assembler.symbols[flag] = flag + "Bit" |