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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:59 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:59 -0800 |
| commit | f1f5dd79bf8c2cf2ef64cc1432a4a0601d475e72 (patch) | |
| tree | 7215bb386591b8ff8d3ce53cefd40599c1a44c2a /src/arch/x86/isa/microasm.isa | |
| parent | 4d4d2883f9c84f0cebec4b65479c11540dbb36f7 (diff) | |
| download | gem5-f1f5dd79bf8c2cf2ef64cc1432a4a0601d475e72.tar.xz | |
X86: Implement the wrcr microop which writes a control register, and some control register work.
--HG--
extra : convert_revision : 3e9daef9cdd0665c033420e5b4f981649e9908ab
Diffstat (limited to 'src/arch/x86/isa/microasm.isa')
| -rw-r--r-- | src/arch/x86/isa/microasm.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index e05582e37..040bb2036 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -113,6 +113,9 @@ let {{ for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() + for reg in range(15): + assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg + for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'): assembler.symbols[flag] = flag + "Bit" |