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authorGabe Black <gblack@eecs.umich.edu>2008-06-12 00:49:50 -0400
committerGabe Black <gblack@eecs.umich.edu>2008-06-12 00:49:50 -0400
commite0c20386ac0f8f54db2e8947793b4c2debabcefc (patch)
treef3aad0978e98724d3ab08054a031ea3887f047f6 /src/arch/x86/isa/microasm.isa
parent2bb8933f789d65f47a322e1384eb2e500699bf14 (diff)
downloadgem5-e0c20386ac0f8f54db2e8947793b4c2debabcefc.tar.xz
X86: Add microops and supporting code to manipulate the whole rflags register.
Diffstat (limited to 'src/arch/x86/isa/microasm.isa')
-rw-r--r--src/arch/x86/isa/microasm.isa5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 78ae34f52..18abdf09b 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2007 The Hewlett-Packard Development Company
+// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
// All rights reserved.
//
// Redistribution and use of this software in source and binary forms,
@@ -135,7 +135,8 @@ let {{
for reg in range(15):
assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg
- for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'):
+ for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \
+ 'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'):
assembler.symbols[flag] = flag + "Bit"
for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',