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authorSteve Reinhardt <stever@eecs.umich.edu>2007-06-21 12:03:22 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2007-06-21 12:03:22 -0700
commiteff122797b5bc735c6d7c797be691c0fa02032e3 (patch)
tree1dd1cef3b2b4e044fece9a406cd0ce97d09a2da7 /src/arch/x86/isa/microasm.isa
parent83af0fdcf57175adf8077c51e9ba872dd2c04b76 (diff)
parent5195500cdf7dc99b5367f91387eef4e9f5b65bfe (diff)
downloadgem5-eff122797b5bc735c6d7c797be691c0fa02032e3.tar.xz
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
Diffstat (limited to 'src/arch/x86/isa/microasm.isa')
-rw-r--r--src/arch/x86/isa/microasm.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index fde430691..50addb33f 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -68,7 +68,7 @@ let {{
import sys
sys.path[0:0] = ["src/arch/x86/isa/"]
from insts import microcode
- print microcode
+ # print microcode
from micro_asm import MicroAssembler, Rom_Macroop, Rom
mainRom = Rom('main ROM')
assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)