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authorGabe Black <gblack@eecs.umich.edu>2007-10-02 22:58:04 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-10-02 22:58:04 -0700
commit06d2d54b57ae9b5f2d9e65445ada5c90721a101e (patch)
tree543db9630e1d00043181a85afe33353348a20a91 /src/arch/x86/isa/microops/fpop.isa
parent3e644b48bbbc3c0c3f3dd6bb158ea7b9c2024424 (diff)
downloadgem5-06d2d54b57ae9b5f2d9e65445ada5c90721a101e.tar.xz
X86: Fix the movfp microop.
--HG-- extra : convert_revision : 23829782a2802a97a05e4dfdb5dd38fbe4165a90
Diffstat (limited to 'src/arch/x86/isa/microops/fpop.isa')
-rw-r--r--src/arch/x86/isa/microops/fpop.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index e9a7cb84f..2919aa277 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -260,7 +260,7 @@ let {{
SetStatus=False, dataSize="env.dataSize"):
super(Movfp, self).__init__(dest, src1, flags, \
spm, SetStatus, dataSize)
- code = 'FpDestReg.uqw = FpSrcReg2.uqw;'
+ code = 'FpDestReg.uqw = FpSrcReg1.uqw;'
else_code = 'FpDestReg.uqw = FpDestReg.uqw;'
cond_check = "checkCondition(ccFlagBits, src2)"