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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-11 09:25:43 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-11 09:25:43 -0500 |
| commit | 6369df59c85870c0975bc881d7b7d612c9dcf15b (patch) | |
| tree | 0037bd2955043db5b60c5b967161ed45d30c5d21 /src/arch/x86/isa/microops/fpop.isa | |
| parent | 3700e5448a947197f16e6da07368cbe5fe783fd6 (diff) | |
| download | gem5-6369df59c85870c0975bc881d7b7d612c9dcf15b.tar.xz | |
x86: Add a separate register for D flag bit
The D flag bit is part of the cc flag bit register currently. But since it
is not being used any where in the implementation, it creates an unnecessary
dependency. Hence, it is being moved to a separate register.
Diffstat (limited to 'src/arch/x86/isa/microops/fpop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/fpop.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index 08a74173c..7acbe04ea 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -215,8 +215,8 @@ let {{ spm, SetStatus, dataSize) code = 'FpDestReg_uqw = FpSrcReg1_uqw;' else_code = 'FpDestReg_uqw = FpDestReg_uqw;' - cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \ - src2)" + cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | \ + ecfBit | ezfBit, src2)" class Xorfp(FpOp): code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;' |