summaryrefslogtreecommitdiff
path: root/src/arch/x86/isa/microops/ldstop.isa
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2007-10-12 16:37:55 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-10-12 16:37:55 -0700
commit9498e536c0231b808669f2bacb4c0628d1ec309a (patch)
tree13edd1623e87077269a03b10a37a66bf61f4f969 /src/arch/x86/isa/microops/ldstop.isa
parent8b35bd6fe79ce069428431a4edbe43b8373f7e87 (diff)
downloadgem5-9498e536c0231b808669f2bacb4c0628d1ec309a.tar.xz
X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all modes. --HG-- extra : convert_revision : ff893eb569313d8aecbfffb47bcbd1c2d65cd393
Diffstat (limited to 'src/arch/x86/isa/microops/ldstop.isa')
-rw-r--r--src/arch/x86/isa/microops/ldstop.isa22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 106a8a0fe..32fefb5fa 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -325,13 +325,13 @@ def template MicroLdStOpConstructor {{
let {{
class LdStOp(X86Microop):
- def __init__(self, data, segment, addr, disp, dataSize):
+ def __init__(self, data, segment, addr, disp, dataSize, addressSize):
self.data = data
[self.scale, self.index, self.base] = addr
self.disp = disp
self.segment = segment
self.dataSize = dataSize
- self.addressSize = "env.addressSize"
+ self.addressSize = addressSize
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, mnemonic
@@ -378,10 +378,10 @@ let {{
exec_output += MicroLoadCompleteAcc.subst(iop)
class LoadOp(LdStOp):
- def __init__(self, data, segment, addr,
- disp = 0, dataSize="env.dataSize"):
+ def __init__(self, data, segment, addr, disp = 0,
+ dataSize="env.dataSize", addressSize="env.addressSize"):
super(LoadOp, self).__init__(data, segment,
- addr, disp, dataSize)
+ addr, disp, dataSize, addressSize)
self.className = Name
self.mnemonic = name
@@ -411,10 +411,10 @@ let {{
exec_output += MicroStoreCompleteAcc.subst(iop)
class StoreOp(LdStOp):
- def __init__(self, data, segment, addr,
- disp = 0, dataSize="env.dataSize"):
+ def __init__(self, data, segment, addr, disp = 0,
+ dataSize="env.dataSize", addressSize="env.addressSize"):
super(StoreOp, self).__init__(data, segment,
- addr, disp, dataSize)
+ addr, disp, dataSize, addressSize)
self.className = Name
self.mnemonic = name
@@ -432,10 +432,10 @@ let {{
exec_output += MicroLeaExecute.subst(iop)
class LeaOp(LdStOp):
- def __init__(self, data, segment, addr,
- disp = 0, dataSize="env.dataSize"):
+ def __init__(self, data, segment, addr, disp = 0,
+ dataSize="env.dataSize", addressSize="env.addressSize"):
super(LeaOp, self).__init__(data, segment,
- addr, disp, dataSize)
+ addr, disp, dataSize, addressSize)
self.className = "Lea"
self.mnemonic = "lea"