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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-27 09:23:50 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-27 09:23:50 -0800 |
| commit | 9dfa3f7f735ead0ada9eb79227f217d0d76e0f49 (patch) | |
| tree | 5c82e9e2dd91f0b808dd74fdce33863a2c6e128b /src/arch/x86/isa/microops/ldstop.isa | |
| parent | 9491debaa623aa0ed148ca4bc810f099058b67a1 (diff) | |
| download | gem5-9dfa3f7f735ead0ada9eb79227f217d0d76e0f49.tar.xz | |
X86: Fix segment limit checks.
Diffstat (limited to 'src/arch/x86/isa/microops/ldstop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/ldstop.isa | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 3bc238174..834b3947f 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -375,6 +375,8 @@ let {{ self.memFlags += " | (CPL0FlagBit << FlagShift)" if prefetch: self.memFlags += " | Request::PF_EXCLUSIVE" + self.memFlags += " | (machInst.legacy.addr ? " + \ + "(AddrSizeFlagBit << FlagShift) : 0)" def getAllocator(self, *microFlags): allocator = '''new %(class_name)s(machInst, macrocodeBlock @@ -439,7 +441,7 @@ let {{ defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;') def defineMicroStoreOp(mnemonic, code, \ - postCode="", completeCode="", mem_flags=0): + postCode="", completeCode="", mem_flags="0"): global header_output global decoder_output global exec_output |