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authorGabe Black <gblack@eecs.umich.edu>2007-11-12 14:37:54 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-11-12 14:37:54 -0800
commitaaa30714b3808a9283cda41bf29e167bf6b8edb0 (patch)
treeadb8b30eb4a363e6b6f8687d730ec85b17c33b8e /src/arch/x86/isa/microops/ldstop.isa
parentada071db53208bf02afee79390d1169130ce99ed (diff)
downloadgem5-aaa30714b3808a9283cda41bf29e167bf6b8edb0.tar.xz
X86: Various fixes to indexing segmentation related registers
--HG-- extra : convert_revision : 3d45da3a3fb38327582cfdfb72cfc4ce1b1d31af
Diffstat (limited to 'src/arch/x86/isa/microops/ldstop.isa')
-rw-r--r--src/arch/x86/isa/microops/ldstop.isa8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 61adde8d1..77152a190 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -123,7 +123,7 @@ def template MicroLoadExecute {{
%(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
- fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment));
+ fault = read(xc, EA, Mem, (%(mem_flags)s) | segment);
if(fault == NoFault)
{
@@ -150,7 +150,7 @@ def template MicroLoadInitiateAcc {{
%(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
- fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment));
+ fault = read(xc, EA, Mem, (%(mem_flags)s) | segment);
return fault;
}
@@ -197,7 +197,7 @@ def template MicroStoreExecute {{
if(fault == NoFault)
{
- fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment));
+ fault = write(xc, Mem, EA, (%(mem_flags)s) | segment);
if(fault == NoFault)
{
%(op_wb)s;
@@ -224,7 +224,7 @@ def template MicroStoreInitiateAcc {{
if(fault == NoFault)
{
- fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment));
+ fault = write(xc, Mem, EA, (%(mem_flags)s) | segment);
if(fault == NoFault)
{
%(op_wb)s;