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authorDerek Hower <drh5@cs.wisc.edu>2010-01-19 15:48:12 -0600
committerDerek Hower <drh5@cs.wisc.edu>2010-01-19 15:48:12 -0600
commit279f179babc9e5663156777c533c06edc91bce9a (patch)
treee6718ee514cc81678491b50562ce8c463c0b20fd /src/arch/x86/isa/microops/ldstop.isa
parent5aa104e072eb20f6aca49b169521b0c2da33c844 (diff)
parent295516a590b6e47c9a881f193027447e500c749c (diff)
downloadgem5-279f179babc9e5663156777c533c06edc91bce9a.tar.xz
merge
Diffstat (limited to 'src/arch/x86/isa/microops/ldstop.isa')
-rw-r--r--src/arch/x86/isa/microops/ldstop.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 912aa3511..afe1ead59 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -157,7 +157,7 @@ def template MicroLoadExecute {{
if (fault == NoFault) {
%(code)s;
- } else if (memFlags & Request::PF_EXCLUSIVE) {
+ } else if (memFlags & Request::PREFETCH) {
// For prefetches, ignore any faults/exceptions.
return NoFault;
}
@@ -374,7 +374,7 @@ let {{
if atCPL0:
self.memFlags += " | (CPL0FlagBit << FlagShift)"
if prefetch:
- self.memFlags += " | Request::PF_EXCLUSIVE"
+ self.memFlags += " | Request::PREFETCH"
self.memFlags += " | (machInst.legacy.addr ? " + \
"(AddrSizeFlagBit << FlagShift) : 0)"