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authorGabe Black <gabeblack@google.com>2017-12-12 17:54:58 -0800
committerGabe Black <gabeblack@google.com>2017-12-13 23:50:53 +0000
commit36d5e8925526b15d1638ac44380e4ada5af16e08 (patch)
treeed561a8a5ca4057467d015d1c6366229824e1bbb /src/arch/x86/isa/microops/ldstop.isa
parenta8f82f545abd27657e19a91dd6b9675a576b116b (diff)
downloadgem5-36d5e8925526b15d1638ac44380e4ada5af16e08.tar.xz
x86: Rework how "split" loads/stores are handled.
Explicitly separate the way the data is represented in the underlying representation from how it's represented in the instruction. In order to make the ISA parser happy, the Mem operand needs to have a single, particular type. To handle that with scalar types, we just used uint64_ts and then worked with values that were smaller than the maximum we could hold. To work with these new array values, we also use an underlying uint64_t for each element. To make accessing the underlying memory system more natural, when we go to actually read or write values, we translate the access into an array of the actual, correct underlying type. That way we don't have non-exact asserts which confuse gcc, or weird endianness conversion which assumes that the data should be flipped 8 bytes at a time. Because the functions involved are generally inline, the syntactic niceness should all boil off, and the final implementation in the binary should be simple and efficient for the given data types. Change-Id: I14ce7a2fe0dc2cbaf6ad4a0d19f743c45ee78e26 Reviewed-on: https://gem5-review.googlesource.com/6582 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/isa/microops/ldstop.isa')
-rw-r--r--src/arch/x86/isa/microops/ldstop.isa51
1 files changed, 15 insertions, 36 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 5ff4f0cea..a3d9c5a70 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -99,8 +99,7 @@ def template MicroLoadExecute {{
%(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
- fault = readMemAtomic(xc, traceData, EA, Mem,
- %(memDataSize)s, memFlags);
+ fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags);
if (fault == NoFault) {
%(code)s;
@@ -145,7 +144,7 @@ def template MicroLoadCompleteAcc {{
%(op_decl)s;
%(op_rd)s;
- getMem(pkt, Mem, %(memDataSize)s, traceData);
+ getMem(pkt, Mem, dataSize, traceData);
%(code)s;
@@ -174,12 +173,10 @@ def template MicroStoreExecute {{
%(code)s;
- if(fault == NoFault)
- {
- fault = writeMemAtomic(xc, traceData, Mem, %(memDataSize)s, EA,
- memFlags, NULL);
- if(fault == NoFault)
- {
+ if (fault == NoFault) {
+ fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA,
+ memFlags, NULL);
+ if (fault == NoFault) {
%(op_wb)s;
}
}
@@ -202,10 +199,9 @@ def template MicroStoreInitiateAcc {{
%(code)s;
- if(fault == NoFault)
- {
- fault = writeMemTiming(xc, traceData, Mem, %(memDataSize)s, EA,
- memFlags, NULL);
+ if (fault == NoFault) {
+ fault = writeMemTiming(xc, traceData, Mem, dataSize, EA,
+ memFlags, NULL);
}
return fault;
}
@@ -561,18 +557,9 @@ let {{
microopClasses[name] = LoadOp
code = '''
- switch (dataSize) {
- case 4:
- DataLow = bits(Mem_u2qw[0], 31, 0);
- DataHi = bits(Mem_u2qw[0], 63, 32);
- break;
- case 8:
- DataLow = Mem_u2qw[0];
- DataHi = Mem_u2qw[1];
- break;
- default:
- panic("Unhandled data size %d in LdSplit.\\n", dataSize);
- }'''
+ DataLow = Mem_u2qw[0];
+ DataHi = Mem_u2qw[1];
+ '''
defineMicroLoadSplitOp('LdSplit', code,
'(StoreCheck << FlagShift)')
@@ -683,17 +670,9 @@ let {{
microopClasses[name] = StoreOp
code = '''
- switch (dataSize) {
- case 4:
- Mem_u2qw[0] = (DataHi << 32) | DataLow;
- break;
- case 8:
- Mem_u2qw[0] = DataLow;
- Mem_u2qw[1] = DataHi;
- break;
- default:
- panic("Unhandled data size %d in StSplit.\\n", dataSize);
- }'''
+ Mem_u2qw[0] = DataLow;
+ Mem_u2qw[1] = DataHi;
+ '''
defineMicroStoreSplitOp('StSplit', code);