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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-27 18:50:51 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-27 18:50:51 -0600 |
| commit | 4eb3b1ed0b0cb5182d92fd56c21b5ca003c0fda5 (patch) | |
| tree | 36e6badd9d0babb125df4cfd138dcfe446ce3433 /src/arch/x86/isa/microops/mediaop.isa | |
| parent | 95b782f60005b58275889e3c5ab2a62ccc7d59c5 (diff) | |
| download | gem5-4eb3b1ed0b0cb5182d92fd56c21b5ca003c0fda5.tar.xz | |
x86: correct error in emms instruction.
Diffstat (limited to 'src/arch/x86/isa/microops/mediaop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/mediaop.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 20e09507e..0f41491f9 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -1506,6 +1506,6 @@ let {{ class Emms(MediaOp): def __init__(self): super(Emms, self).__init__('InstRegIndex(MISCREG_FTW)', - 'InstRegIndex(0)', 'InstRegIndex(0)', 0) + 'InstRegIndex(0)', 'InstRegIndex(0)', 2) code = 'FTW = 0xFFFF;' }}; |