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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:20 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:20 -0600 |
| commit | 7f5463539b291b237647d3eceb7ca0276d487987 (patch) | |
| tree | 89726957ab8e2e3789750530b11474d133a8113a /src/arch/x86/isa/microops/mediaop.isa | |
| parent | 91b00d98a5973d47b831495f5c668bbb185c7a15 (diff) | |
| download | gem5-7f5463539b291b237647d3eceb7ca0276d487987.tar.xz | |
x86: implements emms instruction
Diffstat (limited to 'src/arch/x86/isa/microops/mediaop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/mediaop.isa | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 7178f1f52..20e09507e 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -1502,4 +1502,10 @@ let {{ else if(arg1 == arg2) ccFlagBits = ccFlagBits | ZFBit; ''' + + class Emms(MediaOp): + def __init__(self): + super(Emms, self).__init__('InstRegIndex(MISCREG_FTW)', + 'InstRegIndex(0)', 'InstRegIndex(0)', 0) + code = 'FTW = 0xFFFF;' }}; |