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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:18 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:18 -0800 |
| commit | dc8018a5c3482008232e6faaa2d96cf20aed7485 (patch) | |
| tree | a972ac4544e227397595baf6eeb30e1854f480fc /src/arch/x86/isa/microops/mediaop.isa | |
| parent | c8c82f09a282832d919f7eb073a47be838e65b29 (diff) | |
| download | gem5-dc8018a5c3482008232e6faaa2d96cf20aed7485.tar.xz | |
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
Diffstat (limited to 'src/arch/x86/isa/microops/mediaop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/mediaop.isa | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index e5f04109f..cdb3b4899 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -214,7 +214,7 @@ let {{ if ext is None: self.ext = 0 else: - self.ext = ext + self.ext = ext def getAllocator(self, microFlags): className = self.className @@ -926,7 +926,7 @@ let {{ uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex); uint64_t resBits = arg1Bits + arg2Bits; - + if (ext & 0x2) { if (signedOp()) { int arg1Sign = bits(arg1Bits, sizeBits - 1); @@ -963,7 +963,7 @@ let {{ uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex); uint64_t resBits = arg1Bits - arg2Bits; - + if (ext & 0x2) { if (signedOp()) { int arg1Sign = bits(arg1Bits, sizeBits - 1); @@ -1025,7 +1025,7 @@ let {{ if (ext & 0x4) resBits += (ULL(1) << (destBits - 1)); - + if (multHi()) resBits >>= destBits; @@ -1050,7 +1050,7 @@ let {{ uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex); uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2; - + result = insertBits(result, hiIndex, loIndex, resBits); } FpDestReg_uqw = result; |