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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-12 17:19:14 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-12 17:19:14 +0000 |
| commit | 02732929e8a69fcdda523ebc7aa511d4cdbb0f0e (patch) | |
| tree | 0c4f8c8327b69c0191da08d8ca8ee24b20f37e19 /src/arch/x86/isa/microops/regop.isa | |
| parent | 1a3e668446e4b2d2c61651c9ae58e643c2aa3ad2 (diff) | |
| parent | 0d8d3f988f835e58e5e53b6ee2be871e7bff9132 (diff) | |
| download | gem5-02732929e8a69fcdda523ebc7aa511d4cdbb0f0e.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : 1d2efac895a1c8328026a079e0b319a436325616
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 52c13231c..c2aa27b67 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -231,17 +231,18 @@ let {{ self.ext = 0 def getAllocator(self, *microFlags): - allocator = '''new %(class_name)s(machInst, %(mnemonic)s, - %(flags)s %(src1)s, %(src2)s, %(dest)s, + allocator = '''new %(class_name)s(machInst, "%(mnemonic)s" + %(flags)s, %(src1)s, %(src2)s, %(dest)s, %(setStatus)s, %(dataSize)s, %(ext)s)''' % { "class_name" : self.className, "mnemonic" : self.mnemonic, "flags" : self.microFlagsText(microFlags), "src1" : self.src1, "src2" : self.src2, "dest" : self.dest, - "setStatus" : self.setStatus, + "setStatus" : self.cppBool(self.setStatus), "dataSize" : self.dataSize, "ext" : self.ext} + return allocator class RegOpImm(X86Microop): def __init__(self, dest, src1, imm): @@ -253,17 +254,18 @@ let {{ self.ext = 0 def getAllocator(self, *microFlags): - allocator = '''new %(class_name)s(machInst, %(mnemonic)s, - %(flags)s %(src1)s, %(imm8)s, %(dest)s, + allocator = '''new %(class_name)s(machInst, "%(mnemonic)s" + %(flags)s, %(src1)s, %(imm8)s, %(dest)s, %(setStatus)s, %(dataSize)s, %(ext)s)''' % { "class_name" : self.className, "mnemonic" : self.mnemonic, "flags" : self.microFlagsText(microFlags), "src1" : self.src1, "imm8" : self.imm8, "dest" : self.dest, - "setStatus" : self.setStatus, + "setStatus" : self.cppBool(self.setStatus), "dataSize" : self.dataSize, "ext" : self.ext} + return allocator }}; let {{ @@ -290,7 +292,7 @@ let {{ immCode = matcher.sub("imm8", code) # Build up the all register version of this micro op - iop = InstObjParams(name, Name, 'X86MicroOpBase', {"code" : regCode}) + iop = InstObjParams(name, Name, 'X86MicroopBase', {"code" : regCode}) header_output += MicroRegOpDeclare.subst(iop) decoder_output += MicroRegOpConstructor.subst(iop) exec_output += MicroRegOpExecute.subst(iop) @@ -305,7 +307,7 @@ let {{ # Build up the immediate version of this micro op iop = InstObjParams(name + "i", Name, - 'X86MicroOpBase', {"code" : immCode}) + 'X86MicroopBase', {"code" : immCode}) header_output += MicroRegOpImmDeclare.subst(iop) decoder_output += MicroRegOpImmConstructor.subst(iop) exec_output += MicroRegOpImmExecute.subst(iop) |