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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:56:49 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:56:49 -0700 |
| commit | a238959c3405a18a085d15be07af20a91ff9340d (patch) | |
| tree | f10b8acda8958c147fa32b9f73f9715aba69ba74 /src/arch/x86/isa/microops/regop.isa | |
| parent | 22a5f66820b9c2399898a7ba741ecda49a3c235d (diff) | |
| download | gem5-a238959c3405a18a085d15be07af20a91ff9340d.tar.xz | |
X86: Fix the carry flag for shr.
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index ac380f34b..e86e9f00a 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -680,8 +680,11 @@ let {{ //worry about setting them. ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); //If some combination of the CF bits need to be set, set them. - if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) + if ((ext & (CFBit | ECFBit)) && + shiftAmt <= dataSize * 8 && + bits(SrcReg1, shiftAmt - 1)) { ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + } //Figure out what the OF bit should be. if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) ccFlagBits = ccFlagBits | OFBit; |