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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-06 16:09:28 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-06 16:09:28 -0700 |
| commit | 4478487c372ac79fb98b85f3710ab3c101c82a00 (patch) | |
| tree | dc25c45cb6c86aa99f1286c59468c125585a3ec4 /src/arch/x86/isa/microops/regop.isa | |
| parent | 57da0594157058f9d741dd19a4f08830652789f3 (diff) | |
| download | gem5-4478487c372ac79fb98b85f3710ab3c101c82a00.tar.xz | |
X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones.
--HG--
extra : convert_revision : ee0b5acde08d12c51a5282efb58d1ac72e0779af
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 34 |
1 files changed, 27 insertions, 7 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index dca6d7377..ec6f49424 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -488,13 +488,6 @@ let {{ code = 'DestReg = merge(SrcReg1, op2, dataSize)' else_code = 'DestReg=DestReg;' - class Xorfp(RegOp): - code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' - - class Movfp(CondRegOp): - code = 'FpDestReg.uqw = FpSrcReg2.uqw;' - else_code = 'FpDestReg.uqw = FpDestReg.uqw;' - # Shift instructions class Sll(FlagRegOp): @@ -640,6 +633,33 @@ let {{ class Zext(RegOp): code = 'DestReg = bits(psrc1, imm8-1, 0);' + class Compfp(WrRegOp): + # This class sets the condition codes in rflags according to the + # rules for comparing floating point. + code = ''' + // ZF PF CF + // Unordered 1 1 1 + // Greater than 0 0 0 + // Less than 0 0 1 + // Equal 1 0 0 + // OF = SF = AF = 0 + ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit | + ZFBit | PFBit | CFBit); + if (isnan(FpSrcReg1) || isnan(FpSrcReg2)) + ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit); + else if(FpSrcReg1 < FpSrcReg2) + ccFlagBits = ccFlagBits | CFBit; + else if(FpSrcReg1 == FpSrcReg2) + ccFlagBits = ccFlagBits | ZFBit; + ''' + + class Xorfp(RegOp): + code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' + + class Movfp(CondRegOp): + code = 'FpDestReg.uqw = FpSrcReg2.uqw;' + else_code = 'FpDestReg.uqw = FpDestReg.uqw;' + # Conversion microops class ConvOp(RegOp): abstract = True |