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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-04 23:44:37 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-04 23:44:37 -0700 |
| commit | fea46ee6e3c55e5245f8954a3fa771a6ec3aca84 (patch) | |
| tree | 7487eb97e6ad418a46419b29a92b3540957ebe16 /src/arch/x86/isa/microops/regop.isa | |
| parent | 6c689a3b4b3991342200bb2a433fdf7fbd76b4fc (diff) | |
| download | gem5-fea46ee6e3c55e5245f8954a3fa771a6ec3aca84.tar.xz | |
X86: Implement an SSE xor microop and instruction.
--HG--
extra : convert_revision : 949737d0f5d6fe4aa77cc4680d0c88caab3e8174
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 589113ba3..dca6d7377 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -488,6 +488,9 @@ let {{ code = 'DestReg = merge(SrcReg1, op2, dataSize)' else_code = 'DestReg=DestReg;' + class Xorfp(RegOp): + code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' + class Movfp(CondRegOp): code = 'FpDestReg.uqw = FpSrcReg2.uqw;' else_code = 'FpDestReg.uqw = FpDestReg.uqw;' |