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| author | Vince Weaver <vince@csl.cornell.edu> | 2009-11-11 17:49:09 -0500 |
|---|---|---|
| committer | Vince Weaver <vince@csl.cornell.edu> | 2009-11-11 17:49:09 -0500 |
| commit | 8f6744c19c7d6cf87a207e901503c3435c1ff7a9 (patch) | |
| tree | a557f896130cfd9c14dc271b7169bd58dcd54f8a /src/arch/x86/isa/microops/regop.isa | |
| parent | 5524af83efab8ee502f84987d56306ecd140ab80 (diff) | |
| download | gem5-8f6744c19c7d6cf87a207e901503c3435c1ff7a9.tar.xz | |
X86: add ULL to 1's being shifted in 64-bit values
Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems. On the perl makerand input this
caused some values to be negative that shouldn't have been.
The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index fd1ad6925..0b1f9a96a 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -525,7 +525,7 @@ let {{ code = ''' ProdLow = psrc1 * op2; int halfSize = (dataSize * 8) / 2; - uint64_t shifter = (1ULL << halfSize); + uint64_t shifter = (ULL(1) << halfSize); uint64_t hiResult; uint64_t psrc1_h = psrc1 / shifter; uint64_t psrc1_l = psrc1 & mask(halfSize); @@ -553,7 +553,7 @@ let {{ code = ''' ProdLow = psrc1 * op2; int halfSize = (dataSize * 8) / 2; - uint64_t shifter = (1ULL << halfSize); + uint64_t shifter = (ULL(1) << halfSize); uint64_t psrc1_h = psrc1 / shifter; uint64_t psrc1_l = psrc1 & mask(halfSize); uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); |