diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:58:03 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:58:03 -0700 |
| commit | c087b60af34abb2b496d2308327071c45c1a9a04 (patch) | |
| tree | 12e1603ae78d8d23fb2fbc68267edb44d061bad8 /src/arch/x86/isa/microops/regop.isa | |
| parent | 860f0f835097e884d15069af22efec9c8d766b4e (diff) | |
| download | gem5-c087b60af34abb2b496d2308327071c45c1a9a04.tar.xz | |
X86: Fix the sar carry flag.
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 4d4079f5f..5461223a3 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -711,8 +711,12 @@ let {{ //worry about setting them. ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); //If some combination of the CF bits need to be set, set them. - if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) + uint8_t effectiveShift = + (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); + if ((ext & (CFBit | ECFBit)) && + bits(SrcReg1, effectiveShift - 1)) { ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + } //Use the regular mechanisms to calculate the other flags. ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); |