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authorSteve Reinhardt <steve.reinhardt@amd.com>2016-02-06 17:21:18 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2016-02-06 17:21:18 -0800
commitdc8018a5c3482008232e6faaa2d96cf20aed7485 (patch)
treea972ac4544e227397595baf6eeb30e1854f480fc /src/arch/x86/isa/microops/regop.isa
parentc8c82f09a282832d919f7eb073a47be838e65b29 (diff)
downloadgem5-dc8018a5c3482008232e6faaa2d96cf20aed7485.tar.xz
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
-rw-r--r--src/arch/x86/isa/microops/regop.isa6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 15515ed12..ef0c4cb18 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -238,7 +238,7 @@ let {{
global exec_output
# Stick all the code together so it can be searched at once
- allCode = "|".join((code, flag_code, cond_check, else_code,
+ allCode = "|".join((code, flag_code, cond_check, else_code,
cond_control_flag_init))
allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
cond_control_flag_init))
@@ -786,7 +786,7 @@ let {{
PredecfBit = PredecfBit & ~(ext & ECFBit);
//If some combination of the CF bits need to be set, set them.
- if ((ext & (CFBit | ECFBit)) &&
+ if ((ext & (CFBit | ECFBit)) &&
shiftAmt <= dataSize * 8 &&
bits(SrcReg1, shiftAmt - 1)) {
PredcfofBits = PredcfofBits | (ext & CFBit);
@@ -1018,7 +1018,7 @@ let {{
int msb = bits(DestReg, dataSize * 8 - 1);
int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
//If some combination of the CF bits need to be set, set them.
- if ((ext & (CFBit | ECFBit)) &&
+ if ((ext & (CFBit | ECFBit)) &&
(realShiftAmt == 0) ? origCFBit : CFBits) {
PredcfofBits = PredcfofBits | (ext & CFBit);
PredecfBit = PredecfBit | (ext & ECFBit);