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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-06 16:18:34 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-06 16:18:34 -0700 |
| commit | 389abade01f44ce7204776c0d71f89c8d3177d9d (patch) | |
| tree | 8ce232e25289338e6c404ad80c6f02ef319ae76c /src/arch/x86/isa/microops/regop.isa | |
| parent | 4478487c372ac79fb98b85f3710ab3c101c82a00 (diff) | |
| download | gem5-389abade01f44ce7204776c0d71f89c8d3177d9d.tar.xz | |
X86: Add a square root microop and the SSE sqrt instruction.
--HG--
extra : convert_revision : ddc6e7e95111189d43f75bf84cd3d82433d982b3
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index ec6f49424..57edbb606 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -656,6 +656,9 @@ let {{ class Xorfp(RegOp): code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' + class Sqrtfp(RegOp): + code = 'FpDestReg = sqrt(FpSrcReg2);' + class Movfp(CondRegOp): code = 'FpDestReg.uqw = FpSrcReg2.uqw;' else_code = 'FpDestReg.uqw = FpDestReg.uqw;' |