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author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-19 17:56:06 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-19 17:56:06 +0000 |
commit | d49649279312fe8d05c27a91f94992d8d584c35b (patch) | |
tree | c094438ae522f3438438bf0f5865b9681470608a /src/arch/x86/isa/microops/regop.isa | |
parent | 4486762a8519783aaec7ebe6a391355cd30792e0 (diff) | |
download | gem5-d49649279312fe8d05c27a91f94992d8d584c35b.tar.xz |
Make instructions that are illegal in 64 bit mode not do the wrong thing in 64 bit mode. Also add in more versions of PUSH and POP, and a version of near CALL.
--HG--
extra : convert_revision : 7d8266cdfa54ac25610466b3533d3e9e5433297b
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
-rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index d5fb25cb5..6f86892c3 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -410,4 +410,74 @@ let {{ defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') + # This has it's own function because Wr ops have implicit destinations + def defineMicroRegOpWr(mnemonic, code): + global header_output + global decoder_output + global exec_output + global microopClasses + Name = mnemonic + name = mnemonic.lower() + + # Find op2 in each of the instruction definitions. Create two versions + # of the code, one with an integer operand, and one with an immediate + # operand. + matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") + regCode = matcher.sub("SrcReg2", code) + immCode = matcher.sub("imm8", code) + + # Build up the all register version of this micro op + iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode}) + header_output += MicroRegOpDeclare.subst(iop) + decoder_output += MicroRegOpConstructor.subst(iop) + exec_output += MicroRegOpExecute.subst(iop) + + class RegOpChild(RegOp): + def __init__(self, src1, src2): + super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2) + self.className = Name + self.mnemonic = name + + microopClasses[name] = RegOpChild + + # Build up the immediate version of this micro op + iop = InstObjParams(name + "i", Name, + 'RegOpImm', {"code" : immCode}) + header_output += MicroRegOpImmDeclare.subst(iop) + decoder_output += MicroRegOpImmConstructor.subst(iop) + exec_output += MicroRegOpImmExecute.subst(iop) + + class RegOpImmChild(RegOpImm): + def __init__(self, src1, imm): + super(RegOpImmChild, self).__init__("NUM_INTREGS", src1, imm) + self.className = Name + "Imm" + self.mnemonic = name + "i" + + microopClasses[name + "i"] = RegOpImmChild + + defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') + + # This has it's own function because Rd ops don't always have two parameters + def defineMicroRegOpRd(mnemonic, code): + global header_output + global decoder_output + global exec_output + global microopClasses + Name = mnemonic + name = mnemonic.lower() + + iop = InstObjParams(name, Name, 'RegOp', {"code" : code}) + header_output += MicroRegOpDeclare.subst(iop) + decoder_output += MicroRegOpConstructor.subst(iop) + exec_output += MicroRegOpExecute.subst(iop) + + class RegOpChild(RegOp): + def __init__(self, dest, src1 = "NUM_INTREGS"): + super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS") + self.className = Name + self.mnemonic = name + + microopClasses[name] = RegOpChild + + defineMicroRegOpRd('Rdip', 'DestReg = RIP') }}; |