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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:24:18 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:24:18 -0700 |
| commit | 30e777a5d3829975266ecccac965d2297a5f4985 (patch) | |
| tree | 2363a13c29576b5e3fb027736a817686faaaba67 /src/arch/x86/isa/microops/regop.isa | |
| parent | 802f13e6bdbbc2d6af5a7669a18c0893e5347de6 (diff) | |
| download | gem5-30e777a5d3829975266ecccac965d2297a5f4985.tar.xz | |
X86: Implement microops and instructions that manipulate the flags register.
--HG--
extra : convert_revision : 566841577bf4a98cac0b65292fe0f7daf89a9203
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 3c562efc0..ac88be657 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -615,8 +615,12 @@ let {{ ''') defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;") + defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2') defineMicroRegOpRd('Rdip', 'DestReg = RIP') + defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits') + defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \ + flagCode = genCCFlagBitsLogic) defineMicroRegOpImm('Sext', ''' IntReg val = psrc1; |