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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 15:33:17 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 15:33:17 -0700 |
| commit | 77c0e1d1102af4c023bcd4609022b1600cadfea5 (patch) | |
| tree | 7050d67d8a3aceaedd2695dcfbe2e38580ee7d5a /src/arch/x86/isa/microops/regop.isa | |
| parent | 8384ff7d6c4460a966aec3b65a0af13e71bd76a2 (diff) | |
| download | gem5-77c0e1d1102af4c023bcd4609022b1600cadfea5.tar.xz | |
X86: Create a SeqOp class of microops and make Br one of them.
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index b751b9b4f..d0d7062ff 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -843,10 +843,6 @@ let {{ code = 'RIP = psrc1 + sop2 + CSBase' else_code="RIP = RIP;" - class Br(WrRegOp, CondRegOp): - code = 'nuIP = psrc1 + op2;' - else_code='nuIP = nuIP;' - class Wruflags(WrRegOp): code = 'ccFlagBits = psrc1 ^ op2' |