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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:21:08 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:21:08 -0800 |
| commit | 68300cfb8c6099cc84cb3e544950c0e6a154ff07 (patch) | |
| tree | 7679573d037da9c8e74b43554c8acc5aa451b708 /src/arch/x86/isa/microops/regop.isa | |
| parent | 9842f1ca9d3de48d6bc990248be14b119dca9891 (diff) | |
| download | gem5-68300cfb8c6099cc84cb3e544950c0e6a154ff07.tar.xz | |
X86: Make rdcr use merge and the mov to control register instructions use the right operand size.
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 1349a64c2..7c2feb398 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -967,7 +967,7 @@ let {{ if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { fault = new InvalidOpcode(); } else { - DestReg = ControlSrc1; + DestReg = merge(DestReg, ControlSrc1, dataSize); } ''' |