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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-07-21 19:27:38 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-07-21 19:27:38 -0700 |
| commit | ee6fbdc28b911f0899a93c7711f97b28d22b1039 (patch) | |
| tree | 6aec56669ff767cf19dadd73a3fa6da423e511a7 /src/arch/x86/isa/microops/regop.isa | |
| parent | fc1b7d62b7e8e5cf59956875720dbd1deb68af93 (diff) | |
| download | gem5-ee6fbdc28b911f0899a93c7711f97b28d22b1039.tar.xz | |
Implement rotate with carry microops.
--HG--
extra : convert_revision : 1d7ff6611e5b4766a5257c1e73681fabbe5f6d76
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 1f4de5642..dbbe11c90 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -499,6 +499,19 @@ let {{ DestReg = DestReg; ''') defineMicroRegOp('Rcr', ''' + uint8_t shiftAmt = + (op2 & ((dataSize == 8) ? mask(4) : mask(3))); + if(shiftAmt) + { + CCFlagBits flags = ccFlagBits; + uint64_t top = flags.CF << (dataSize * 8 - shiftAmt); + if(shiftAmt > 1) + top |= SrcReg1 << (dataSize * 8 - shiftAmt - 1); + uint64_t bottom = bits(SrcReg1, dataSize * 8, shiftAmt); + DestReg = merge(DestReg, top | bottom, dataSize); + } + else + DestReg = DestReg; ''') defineMicroRegOp('Rol', ''' uint8_t shiftAmt = @@ -514,6 +527,21 @@ let {{ DestReg = DestReg; ''') defineMicroRegOp('Rcl', ''' + uint8_t shiftAmt = + (op2 & ((dataSize == 8) ? mask(4) : mask(3))); + if(shiftAmt) + { + CCFlagBits flags = ccFlagBits; + uint64_t top = SrcReg1 << shiftAmt; + uint64_t bottom = flags.CF << (shiftAmt - 1); + if(shiftAmt > 1) + bottom |= + bits(SrcReg1, dataSize * 8 - 1, + dataSize * 8 - shiftAmt + 1); + DestReg = merge(DestReg, top | bottom, dataSize); + } + else + DestReg = DestReg; ''') defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;") |