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authorCurtis Dunham <Curtis.Dunham@arm.com>2014-05-09 18:58:46 -0400
committerCurtis Dunham <Curtis.Dunham@arm.com>2014-05-09 18:58:46 -0400
commit7f1603d20728d7990d1d304bbdb6abdfb7eb53d7 (patch)
tree1e7b8267b063cdf10c8180757b6b2f002dea8898 /src/arch/x86/isa/microops/seqop.isa
parenteb61f0123b992236b3ef8331ed35d5954a62a44d (diff)
downloadgem5-7f1603d20728d7990d1d304bbdb6abdfb7eb53d7.tar.xz
arch: remove inline specifiers on all inst constrs, all ISAs
With (upcoming) separate compilation, they are useless. Only link-time optimization could re-inline them, but ideally feedback-directed optimization would choose to do so only for profitable (i.e. common) instructions.
Diffstat (limited to 'src/arch/x86/isa/microops/seqop.isa')
-rw-r--r--src/arch/x86/isa/microops/seqop.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index d60ddced7..72c28b1fe 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -84,7 +84,7 @@ def template SeqOpExecute {{
}};
output decoder {{
- inline SeqOpBase::SeqOpBase(
+ SeqOpBase::SeqOpBase(
ExtMachInst machInst, const char * mnemonic, const char * instMnem,
uint64_t setFlags, uint16_t _target, uint8_t _cc) :
X86MicroopBase(machInst, mnemonic, instMnem, setFlags, No_OpClass),
@@ -94,7 +94,7 @@ output decoder {{
}};
def template SeqOpConstructor {{
- inline %(class_name)s::%(class_name)s(
+ %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
uint64_t setFlags, uint16_t _target, uint8_t _cc) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,